Texas Instruments MSP50C6xx User Manual Download Page 197

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Individual Instruction Descriptions

4-111

Assembly Language Instructions

Opcode

Instructions

Jcc pma16

Not

pma16

Jcc pma16

Rx++

Not

pma16

Jcc pma16

Rx––

Not

pma16

Jcc pma16, Rx++R5

Not

pma16

cc names

Description

cc name

Not cc name

Description

True condition (Not true condition)

Conditional on ZF=1 (Not condition ZF=0)

Conditional on SF=1 (Not condition SF=0)

Conditional on CF=1 (Not condition CF=0)

Conditional on ZF=0 and CF=0 (Not condition ZF

≠

0 or CF

≠

Conditional on ZF=0 and CF=1 (Not condition ZF

≠

0 or CF

≠

Conditional on SF=0 and ZF=0 (Not condition SF

≠

0 or ZF

≠

Conditional if ZF=1 and OF=0 (Not condition ZF

≠

1 or OF

≠

Conditional if OF=1 (Not condition OF=0)

RNC

Conditional on RCF=1 (Not condition RCF=0)

RNA

Conditional on RZF=0 and RCF=1 (Not condition RZF

≠

0 or RCF

≠

RNE

Conditional on RZF=1 (Not condition RZF=0)

RZP

RNZP

Conditional on value of Rx=0 (Not condition Rx

≠

RLZP

RNLZP

Conditional on MSB of Rx=1. (Not condition MSB of Rx=0)

Conditional on ZF=0 and SF=1 (Not condition ZF

≠

0 or SF

≠

reserved

TF1

NTF1

Conditional on TF1=1 (Not condition TF1=0)

TF2

NTF2

Conditional on TF2=1 (Not condition TF2=0)

TAG

NTAG

Conditional on TAG=1 (Not condition TAG=0)

IN1

NIN1

Conditional on IN1=1 status. (Not condition IN1=0)

IN2

NIN2

Conditional on IN2=1 status. (Not condition IN2=0)

Unconditional

reserved

XNZ

Conditional on XZF=1 (Not condition XZF=0)

XNS

Conditional on XSF=1 (Not condition XSF=0)

XNG

Conditional on XSF=0 and XZF=0 (Not condition XSF

≠

0 or XZF

≠

reserved

Summary of Contents for MSP50C6xx

Page 1: ...MSP50C6xx Mixed Signal Processor User s Guide Mixed Signal Products SPSU014A Printed on Recycled Paper...

Page 2: ...parameters of each device is not necessarily performed except those mandated by government requirements Customers are responsible for their applications using TI components In order to minimize risks...

Page 3: ...oduction to the MSP50C6xx Chapter 2 MSP50C6xx Architecture Chapter 3 Peripheral Functions Chapter 4 Assembly Language Instructions Chapter 5 Code Development Tools Chapter 6 Applications Chapter 7 Cus...

Page 4: ...ddress Square brackets and identify an optional parameter If you use an optional parameter you specify the information within the brackets you don t enter the brackets themselves Here s an example of...

Page 5: ...of a caution statement A caution statement describes a situation that could potentially damage your software or equipment This is an example of a warning statement A warning statement describes a situ...

Page 6: ...vi...

Page 7: ...ss Unit 2 11 2 3 1 RAM Configuration 2 12 2 3 2 Data Memory Addressing Modes 2 13 2 4 Program Counter Unit 2 14 2 5 Bit Logic Unit 2 14 2 6 Memory Organization RAM and ROM 2 15 2 6 1 Memory Map 2 15 2...

Page 8: ...tion 4 2 4 2 System Registers 4 2 4 2 1 Multiplier Register MR 4 2 4 2 2 Shift Value Register SV 4 2 4 2 3 Data Pointer Register DP 4 2 4 2 4 Program Counter PC 4 2 4 2 5 Top of Stack TOS 4 3 4 2 6 Pr...

Page 9: ...10 Input Output Instructions 4 59 4 11 Special Filter Instructions 4 59 4 12 Conditionals 4 69 4 13 Legend 4 70 4 14 Individual Instruction Descriptions 4 74 4 15 Instruction Set Encoding 4 189 4 16...

Page 10: ...2 6 2 Initializing the MSP50C6xx 6 4 6 2 1 File init asm 6 5 6 3 TI TALKS Example Code 6 8 6 4 RAM Overlay 6 9 6 4 1 RAM Usage 6 9 6 4 2 RAM Overlay 6 10 6 4 3 Adding Customer Variables 6 10 6 4 4 Com...

Page 11: ...eration 4 3 4 2 Relative Flag Addressing 4 19 4 3 Data Memory Organization and Addressing 4 45 4 4 Data Memory Example 4 47 4 5 FIR Filter Structure 4 59 4 6 Setup and Execution of MSP50P614 MSP50C614...

Page 12: ...Increment and Auto Decrement Modes 4 11 4 7 Flag Addressing Field flagadrs for Certain Flag Instructions Class 8a 4 12 4 8 Initial Processor State for the Examples Before Execution of Instruction 4 13...

Page 13: ...4 44 4 39 Class 9d Instruction Description 4 44 4 40 Data Memory Address and Data Relationship 4 46 4 41 MSP50P614 MSP50C614 Computational Modes 4 50 4 42 Hardware Loops in MSP50P614 MSP50C614 4 54 4...

Page 14: ...xiv...

Page 15: ...gives the MSP50C6xx unprecedented speed and computational flexibility compared with previous devices of its type The MSP50C6xx supports a variety of speech and audio coding algorithms providing a ran...

Page 16: ...C and ADPCM Contains 32K words onboard ROM 2K words reserved Up to 2 36 Mbits of internal data ROM for speech storage 640 words RAM Up to 64 input output pins Direct speaker driver 32 One bit comparat...

Page 17: ...f applications incorporating flexible I O and high quality speech Consumer Education Toys and Games Electronic Learning Aids Appliances Talking Dictionaries Talking Clocks Language Translators Navigat...

Page 18: ...the rate of code execution is limited by the speed of the PC parallel port Any MSP50C6xx MSP50P614 can be used in this debugging mode The MSP50P614 EPROM must be programmed to debug the code in real t...

Page 19: ...Ohm PDM Initialization Logic OSC Reference Resistor Trimmed 32 kHz nominal Crystal Referenced 32 768 kHz PLL Filter or or Scan Interface Power P614 only VDD VPP VSS 5 5 EP ROM 32k x 16 1 bit Test Area...

Page 20: ...divided into two areas 1 The lower 2K words are re served by Texas Instruments for a built in self test 2 the upper 30K is for user program data The data memory is internal static RAM The RAM is confi...

Page 21: ...ns The peripheral consists of five 8 bit wide general purpose I O ports one 8 bit wide dedicated input port and one 16 bit wide dedicated output port The general purpose I O ports are bit wise program...

Page 22: ...ome applications The diode provides a lower impedance path for the capacitor to discharge when power is removed This make the circuit more reliable when power is removed and quickly reapplied Figure 1...

Page 23: ...s The MSP50C601 can provide up to 24 minutes the MSP50C605 can provide up to 37 minutes and the MSP50C604 can provide up to 6 5 minutes of uninterrupted speech The MSP50C604 is de signed to support sl...

Page 24: ...1 10...

Page 25: ...n interrupt system timers clock control mech anism and various low power modes Topic Page 2 1 Architecture Overview 2 2 2 2 Computation Unit 2 5 2 3 Data Memory Address Unit 2 11 2 4 Program Counter U...

Page 26: ...ipulation A unique accumulator register file provides additional scratch pad memory and mini mizes memory thrashing for many operations Five different addressing modes and many short direct references...

Page 27: ...ster CTRL Interrupt Inputs Interrupt Processor Serial Interface Register Oscillator Register Timer Period PRD1 and PRD2 Timer Register TIM1 and TIM2 AP0 AP3 Accumulator Pointer Incrementor 1 Periphera...

Page 28: ...AC10 AC9 AC8 AC15 AC14 AC13 AC12 AC19 AC18 AC17 AC16 AC23 AC22 AC21 AC20 AC27 AC26 AC25 AC24 AC31 AC30 AC29 AC28 AP3 AP2 AP1 AP0 5 Internal Databus 16 bit Shift Value SV Multiplier Register MR 17 bit...

Page 29: ...on cycle The sign bit within each operand is bit 16 and its value extends from bit 0 LSB to bit 15 MSB The sign bit for either operand multiplier or multiplicand can assume a positive value zero or a...

Page 30: ...output result is 32 bit On the other hand if the status bit FM multiplier shift mode is SET then the multiplier operand 0000000010000000 is left shifted once to form a 17 significant bit operand 0000...

Page 31: ...rithmetic Logic Unit The arithmetic logic unit is the focal point of the computational unit where data can be added subtracted and compared Logical operations can also be performed by the ALU The basi...

Page 32: ...ons are addition subtraction and load add to zero The logical operations are AND OR XOR and NOT Comparison includes equal to and not equal to The compare operations may be used with constant memory or...

Page 33: ...C31 For multiply accumulate operations 2 2 2 2 Accumulator Pointer Block There are four 5 bit registers which are used to store pointers to members of the accumulator block The accumulator pointers AP...

Page 34: ...es in one of two forms 1 DIRECT REFERENCE 0 31 AC Register 2 INDIRECT REFERENCE 0 15 points to 0 15 0 15 OFFSET points to 16 31 15 31 OFFSET points to 0 15 AP registers are served by a 5 bit processor...

Page 35: ...or register Refer to Chapter 4 Assembly Language Instructions for more de tails The ALU s accumulator block functions as a small workspace which elimi nates the need for many intermediate transfers to...

Page 36: ...cally the flag bit directs complex branch conditions associated with certain instructions The flag bit is also used by the computational unit for signed or unsigned arithmetic operations see Section 2...

Page 37: ...flags are located at fixed locations in the first 64 RAM addresses and 2 flag relative address whereby a reference is made relative to the current PAGE R6 The relative address supports 64 different fl...

Page 38: ...Address Unit The hardware loop counter controls the execution of repeated instructions using one of two modes 1 consecutive iterations of a single instruction following the repeat RPT instruction or 2...

Page 39: ...ts of the 17 bit RAM are used for the data value while the extra bit is used as a status flag The C6xx does not have the capability to execute instructions directly from external memory However additi...

Page 40: ...ata 0x30 DAC data 0x34 DAC ctrl 0x38 IntGenCtrl 0x39 IFR 0x3A PRD1 0x3B TIM1 0x3D ClkSpdCtrl 0x3E PRD2 0x3F TIM2 0x2F RTRIM Unusable Interrupt Vectors reserved RESET vector 0x7FF8 0x7FFE 0x7FFF Shaded...

Page 41: ...ddress Width of Location Allowable Access Control Register Name Abbreviation State after RESET LOW Section for Reference 0x00 8 bits Read Write I O port A data PA0 7 Data unknown 0x04 8 bits Read Writ...

Page 42: ...upt causes the program counter to branch to a specific location The destination location is stored programmed in the interrupt vector which resides in an up per address of ROM The following table list...

Page 43: ...scheme is composed of two levels both of which prevent the ROM contents from being read Protection may be applied to the entire program memory or it can be applied to a block of memory beginning at a...

Page 44: ...fields The remainder of the 17 bit word is broken into three single bit fields which are reserved for future use Block Protection Word address 0x7FFE 17 bit wide location WRITE only 16 15 14 13 12 11...

Page 45: ...ction Mode When applying the block protection mode bits FM5 through FM0 must be programmed as the logical inverse of bits TM5 through TM0 respectively Across the span of the 32k word ROM space there a...

Page 46: ...acro call vectors are similar to CALL instructions except they take an 8 bit address The upper 8 bits is always 7Fh See Section 4 14 84 VCALL for more information on the VCALL instruction 2 7 Interrup...

Page 47: ...T7 may be associated instead with the Comparator function if the Comparator Enable bit has been set Refer to Section 3 3 Comparator for details Individual interrupts are enabled or disabled for servic...

Page 48: ...ntually the program returns to whatever point it was before the first interrupt service branch When an interrupt service branch is taken the global interrupt enable is automatically cleared by the cor...

Page 49: ...T INT Flag bits IFR Associated With the Interrupt Trigger Event Interrupt Flag Register 0x39 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 CLEAR BIT INT Mask bits IMR Specific Enable for Interrupt Service I...

Page 50: ...illator Theoscillatorisdesignedtorunnominallyat32kHz IthasalowVDD coefficient and a low temperature coefficient refer to the data sheet The reference resistor is mounted externally across pins OSCIN a...

Page 51: ...le refer to the data sheet in 65 536 kHz steps The maximum required CPU clock frequency for the C6xx is 8 MHz over the entire VDD range This rate applies to the speed of the core processor Higher CPU...

Page 52: ...mmediately after a RESET LOW to HIGH and regardless of whether a resistor or a crystal is installed across OSCIN OSCOUT the C6xx does not have a reference oscillator running In the absence of a refere...

Page 53: ...or more information regarding the C6xx s reduced power modes Note Reference Oscillator Stopped by Programmed Disable If the reference oscillator is stopped by a programmed disable then on re enable th...

Page 54: ...used to obtain a program matic increase or decrease in the speed of the RTO reference The default val ue for the adjustment after RESET low is all zeros The zero value generates the slowest programma...

Page 55: ...T1 is triggered by the underflow of TIMER1 and the interrupt INT2 is triggered by the underflow of TIMER2 INT1 and INT2 are the second and third highest priority interrupts in the C6xx Refer to Sectio...

Page 56: ...urce is either a resistor trimmed oscillator RTO or a crystal oscillator CRO Both reference oscillators are designed to run at a nominal 32 kHz Refer to Section 2 9 Clock Control for more information...

Page 57: ...th the desired period value ahead of time This prepares TIM2 for counting and also loads the period regis ter PRD2 with its value 4 Be sure the TIMER2 interrupt INT2 has been enabled for service set b...

Page 58: ...will be impossible to wake from sleep unless certain controls are set appropriately before going to sleep In those cases only the hardware RESET low to high will bring the device back into its normal...

Page 59: ...clocks run during sleep unless the TIMER source is linked to the reference oscillator Section 2 8 Time Registers These relationships are shown explicitly as a function of the reduced power mode in Tab...

Page 60: ...ower Modes deeper sleep relatively less power Control Bit Label for Control Bit LIGHT MID DEEP Idle state clock control bit 10 ClkSpdCtrl register 0x3D A 0 1 1 Enable reference oscillator bit 09 CRO o...

Page 61: ...operation The time delay required for the CRO to start is greater than the time delay required for the RTO to start There are a number of ways to wake the C6xx from the IDLE induced sleep state The va...

Page 62: ...s LIGHT MID DEEP Timer interrupts TIMER1 and TIMER2 Assuming respective IMR bit is set Assuming ARM bit is set as in C A B C If TIMER is running then Underflow wakes device No wake up from TIMER Exter...

Page 63: ...ruction If the global interrupt enable is CLEAR before going to sleep then the programmed interrupt can still wake the device provided that the respective IMR and ARM bits are set as in Table 2 3 The...

Page 64: ...nsists of two phases with non overlap protection A fully static implementation eliminates pre charge time on busses or in memory blocks This design also results in a very low power dissipation Figure...

Page 65: ...control ports general purpose I O ports interrupt control registers compara tor and digital to analog DAC control mechanisms Topic Page 3 1 I O 3 2 3 2 Digital to Analog Converter DAC 3 9 3 3 Comparat...

Page 66: ...e byte wide The pins within these ports can be individually programmed as input or output in any combination The selection is made by clearing or setting the appropriate bit in the associated control...

Page 67: ...registers is initialized to 0x00 when the RESET pin is taken low This puts all of the programmable I O pins into an input state This condition is maintained after RESET is taken high and until the con...

Page 68: ...arator for details Port D0 is connected to the branch condition COND1 Port D1 is connected to the branch condition COND2 assuming the comparator is disabled Please refer to Section 3 1 4 Branch on D P...

Page 69: ...ght port F input pins see Section 3 1 5 Internal and External Interrupts The F port input pins are gated through an eight input AND gate such that any input pin going low causes the output of the AND...

Page 70: ...table lists the four possible logical states for D0 and D1 along with the software instructions affected by them D0 1 COND1 TRUE CIN1 CNIN1 JIN1 JNIN1 has its conditional call taken has its conditiona...

Page 71: ...toggled high to low no interrupt is detected at the toggling pin After all F port pins have been brought high again then it is possible for a new INT5 trigger to occur INT0 is an internal interrupt h...

Page 72: ...t pin goes from all high to low INT6 0x7FF6 PD4 Rising edge 7th Port D4 goes high INT7 0x7FF7 PD5 Falling edge Lowest Port D5 goes low All F port pins must be high previous to one or more going low IN...

Page 73: ...hese are 7 2 kHz 8 kHz 10 kHz and 11 025 kHz Other sampling rates however may also be possible From the MC to the PDM clock there is an optional divide by two in frequency This option is controlled by...

Page 74: ...off Data values are output to the DAC by writing to the DAC data register address 0x30 The highest priority interrupt INT0 is generated at the sampling rate governed by the ClkSpdCtrl and the DAC cont...

Page 75: ...lp to ensure that the audible artifacts of wrap around do not occur 3 2 3 PDM Clock Divider The pulse density modulation rate is determined by the master clock The PDM rate may be set equal to the rat...

Page 76: ...tation then a return to the main program As stated previously the maximum ensured CPU clock frequency for the MSP50C6xx operates over the entire VDD range This rate applies to the speed of the core pr...

Page 77: ...bits 1 1x 0x 0F 2 10 2 10 1 05 8 19 128 128 2x 0x 1E 4 06 4 06 2 03 15 87 128 256 4x 0x 3E 8 26 8 26 4 13 32 26 128 512 8x 0x 7C 16 38 16 38 8 19 64 00 128 1024 0 1x 0x 1E 4 06 2 03 2 03 7 94 256 256...

Page 78: ...62 2 62 1 31 10 24 128 128 2x 0x 26 5 11 5 11 2 56 19 97 128 256 4x 0x 4D 10 22 10 22 5 11 39 94 128 512 8x 0x 9B 20 45 20 45 10 22 79 87 128 1024 0 1x 0x 26 5 11 2 56 2 56 9 98 256 256 2x 0x 4D 10 22...

Page 79: ...ignored has its conditional call taken JIN2 JNIN2 has its conditional jump ignored has its conditional jump taken 3 Comparator transition FALSE to TRUE VPD5 rises above VPD4 INT6 trigger event If inte...

Page 80: ...th TIMER1 TIMER1 can be started by the falling edge of the comparator The INT6 flag must be cleared and the TIMER1 ENABLE must be cleared before the event Figure 3 2 Relationship Between Comparator In...

Page 81: ...4 INT7 is triggered by PD5 falling below PD4 IntGenCtrl 0x38 bit 6 must be 1 IntGenCtrl 0x38 bit 7 must be 1 TIMER1 may be started by PD5 rising above PD4 TIMER1 will be stopped by PD5 falling below P...

Page 82: ...pt mask register CE Comparator enable AR ARM bit PD Pulse density clock PDMCD EP Enable pullup resistors on port F D5 port D5 falling edge D4 port D4 rising edge PF any port F falling edge D3 port D3...

Page 83: ...13 yields a PDM rate equal to the rate of the master clock see Section 3 2 3 PDM Clock Divider Bit 14 is the ARM bit If the master clock has been suspended during sleep then the ARM bit must be set be...

Page 84: ...some delay on the RESET pin s low to high transition This delay helps to en sure that the MSP50C6xx initialization occurs after the power supply has had time to stabilize between VDD MIN and VDD MAX V...

Page 85: ...l Interrupts are disabled I O Ports A through E and output Port G have the same state as in RESET low All pull up resistors on input Port F are disabled DAC circuitry is disabled no PDM pulsing Both T...

Page 86: ...multiplication disabled allows unsigned fractional integer arithmetic 4 IM 0 Global interrupt enable bit 5 reserved Reserved for future use 6 XZF Transfer equal to zero status bit 7 XSF Transfer sign...

Page 87: ...ntax and Addressing Modes 4 8 4 4 Instruction Classification 4 22 4 5 Bit Byte Word and String Addressing 4 44 4 6 MSP50P614 MSP50C614 Computational Modes 4 49 4 7 Hardware Loop Instructions 4 53 4 8...

Page 88: ...shift instructions the multiplier operand decodes a 4 bit value in the shift value register SV to a 16 bit value For example a value of 7H in the SV register is decoded to a multiplier operand of 0000...

Page 89: ...er R7 The MSP50P614 MSP50C614 hardware uses TOS register for very efficient returns from CALL instructions Figure 4 1 shows the operation of the TOS register When call instructions are executed the ol...

Page 90: ...have offset accumulators AC16 AC31 and vice versa At any one time four accumulators can be selected through accumulator pointer registers AP0 AP3 see section 4 2 9 Some instructions can specify offse...

Page 91: ...ons can be performed on accumulator pointers Bit Bits 16 5 4 3 2 1 0 AP0 AP3 Not used Points to An n val b0 b4 4 2 10 Indirect Register R0 R7 Indirect registers R0 R7 are 16 bit registers that are use...

Page 92: ...tional modes Condition bits and flags are used for conditional branches calls and flag instructions Flags and status condition bits are stored in the upper 10 bits of the 17 bit status register MOV in...

Page 93: ...lator and Rx registers 7 XSF Transfer x sign status flag bit In transfer instructions the sign bit of the value is copied to this bit if the destination is not accumulator or Rx registers 8 RCF Indire...

Page 94: ...e execution of an instruction Op tional or not used for some instructions Destination is also used as both a source and a destination for some instructions If a destination is specified it must always...

Page 95: ...gnificant data word in memory String data fetches using the indirect with post modification addressing mode and writes the modified address back to the indirect register at each cycle of the string Th...

Page 96: ...epeat addressing mode encoding adrs Relative Addressing Modes Clocks clk Words w Repeat Operation clk adrs 7 6 5 4 3 2 1 0 Modes clk w clk am Rx x 0 7 pm Direct 2 2 nR 4 dma16 0 0 0 Rx 0 0 Short relat...

Page 97: ...set7 next A name R6 offset7 src next A Selects PAGE R6 register as the base address and adds a 7 bit positive address offset from operand field b6 b0 This permits the relative addressing of 128 bytes...

Page 98: ...ddress from the indirect register R6 If bit 0 of these instructions is 0 then bits 1 to 6 of the opcode are taken as the bit address starting from data memory location 0000h If bit 0 is 1 then bits 1...

Page 99: ...0x0200 R2 0x0540 R3 0x03E2 R4 0x0000 R5 2 R6 0x03E4 R7 0x0100 AC2 0x13F0 AC1 0x0007 AC17 0x0112 AC20 0x3321 AC3 0xFEED AC28 0x11A2 AC29 0xAB AC19 0x1200 MR 0x1A15 data memory address data word address...

Page 100: ...4 8 before execution of this instruc tion Preincrement AP1 After preincrement A1 is AC22 and A1 is AC6 The content of data memory location 0x01F2 0x12AC is then loaded to accumu lator AC22 offset of...

Page 101: ...post decrement Rx after use Address Memory Operand R5 Rx x 0 7 Note that the Rx registers treats data memory as a series of bytes Therefore when a word is loaded Rx increments by 2 Rx decrements by 2...

Page 102: ...s instruc tion Store the lower 8 bits of A3 AC29 in the data memory byte address pointed to by R7 R7 is then incremented by one Notice that to find the word address divide the address in R7 by 2 Final...

Page 103: ...is AC12 and A2 is AC28 Store AC28 in the data memory byte location R2 R5 The values in R2 and R5 are unchanged Final result 0x02A1 0x11A2 Example 4 3 19 ADD A0 A0 R4 R5 A Refer to the initial process...

Page 104: ...elative Long relative addressing selects one of the 8 address registers Rx as a base value and adds the value of the second word operand The base address reg ister is not modified Syntax name dest src...

Page 105: ...7th bit This should not be confused with byte ad dresses and word addresses Figure 4 2 Relative Flag Addressing Address R6 PAGE register 6 Bit positive offset Operand Syntax name dest src Global Flag...

Page 106: ...2 sets the TAG bit of RAM word two STAG and RTAG use RAM byte addresses to specify which TAG to set or clear This immediately causes confusion since there are 1280 bytes and only 640 TAGs What happen...

Page 107: ...orm as you would expect The TAG bit is set at the RAM variable ram1 The TAG bit is set in the STAT register when the MOV instruction executes Finally ram1 s TAG bit is cleared The next two instruction...

Page 108: ...estination accumulator if this bit is 1 A Can be either A or A based on the opcode or instruction A Select offset accumulator as source if this bit is 1 adrs Addressing mode bits am Rx pm See Table 4...

Page 109: ...se bits are not related to any addres sing modes Rx Indirect register bits as described in Table 4 3 s Represents string mode if 1 otherwise normal mode x Don t care Instructions on the MSP50P614 MSP5...

Page 110: ...ry references with R5 operating on Rx 5 General mMemory reference instructions 6 I O port and memory reference instructions A Port memory reference B Port accumulator reference 7 Program control instr...

Page 111: ...0 1 0 0 An C9a 0 Rx 1 1 Class 9b 1 1 1 1 1 1 0 C9a k Class 9c 1 1 1 1 1 0 1 An 0 C9c x imm5 Class 9d 1 1 1 1 1 1 1 1 0 C9d 0 0 0 0 ENDLOOP n 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 n NOP 1 1 1 1 1 1 1 1 1 1 1...

Page 112: ...rence to offset accumulators in Class 1b instructions the execution operates on memory and accumulators All other modes of control string preincrement predecrement AP data memory addressing modes etc...

Page 113: ...ed on the LSB of the address Transfer status is modified 0 1 0 1 Reserved N A 0 1 1 0 CMP An adrs CMPS An adrs Store the arithmetic status of the contents of adrs subtracted from accumulator into the...

Page 114: ...16 bits to the accumulator and latch the upper 16 bits in PH ALU status is modified 1 1 1 1 MULSPL An adrs MULSPLS An adrs Multiply the MR register by the contents of adrs and subtract the lower 16 b...

Page 115: ...able 4 17 Class 2a Instruction Description C2a Mnemonic Description 0 0 0 ADDB An imm8 Add an 8 bit positive constant to the accumulator and store the result in the accumulator ALU status is modified...

Page 116: ...ogical exclusive OR a long constant with accumulator A 0 or 1 Store the result to accumulator A 0 or 1 ALU status is modified 1 1 1 MOV MR imm16 next A Load a long constant to MR in signed mode No cha...

Page 117: ...ter ALU status is modified based on the lookup value 0 0 0 1 1 ZAC An next A ZACS An Zero accumulator A 0 or 1 ALU status is modified 0 0 1 0 0 SUB An An An next A SUB An An An next A SUBS An An An SU...

Page 118: ...oduct high register to accumulator or to offset accumulator and store the result into accumulator A 0 or 1 ALU status is modified The string bit causes an add with carry status CF 0 1 1 1 0 MOV An PH...

Page 119: ...or offset accumulator A 0 add lower 16 bits of product to offset accumulator A 1 or accumulator A 0 and store to accumulator A 0 or offset accumulator A 1 Latch upper 16 bits in PH ALU status is modif...

Page 120: ...transfers to and from memory In indirect mode any one auxiliary register can serve as the address for loading and storing the con tents of another Subclass 4b instructions provide some basic arithmet...

Page 121: ...Rx 8 bit positive constant into RZF and RCF bits of the STAT register Rx remains unchanged Table 4 24 Class 4c Instruction Description C4c Mnemonic Description 0 0 ADD Rx imm16 Add 16 bit positive co...

Page 122: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Class 5 1 1 0 1 C5 adrs RET 1 1 0 1 1 1 1 0 0 0 1 1 1 1 1 1 0 IRET 1 1 0 1 1 1 1 0 1 0 1 1 1 1 1 1 0 Table 4 27 Class 5 Instruction Description C5 Mnemonic Descr...

Page 123: ...adrs Only the lower 8 bits are loaded Transfer status modified 1 0 1 n n MOV APn adrs Load lower 5 bits with content of data memory location referred by addressing mode adrs to accumulator pointer AP...

Page 124: ...eral functions and those that serve external pins For subclass 6b IN and OUT provide bidirectional transfers between the same port address 16 and accumulator In addition IN and OUT instructions in cla...

Page 125: ...until another instruc tion that affects them is executed In addition to call a macro call instruction is included This instruction is similar to an unconditional call instruction When executed it push...

Page 126: ...tional on ZF 0 and CF 1 0 0 1 0 1 G NG Conditional on SF 0 and ZF 0 0 0 1 1 0 E NE Conditional if ZF 1 and OF 0 0 0 1 1 1 O NO Conditional if OF 1 0 1 0 0 0 RC RNC Conditional on RCF 1 0 1 0 0 1 RA RN...

Page 127: ...ngle bit decisions and constructing a logical statement through a branch decision tree the program can sequentially combine several status conditions to directly construct a final logic value TF1 or T...

Page 128: ...rom data memory referred by flag addressing mode flagadrs to 0 Table 4 32 SFLAG flagadrs Set flag bit 17th bit from data memory referred by flag addressing mode flagadrs to 1 Table 4 34 Class 8b Instr...

Page 129: ...ication between two indirect addressed data memory buffers into a 32 bit accumulator Circular buffer operation Executes in 2 instruction cycles Rx and R x 1 automatically increments by 2 per tap 1 0 C...

Page 130: ...in status register to 0 disabling sign extension mode 1 1 0 0 SFM Sets FM in status register to 1 enabling multiplier shift mode for signed fractional arithmetic 1 1 0 1 RFM Sets FM in status registe...

Page 131: ...assumed to be zero Instructions that operate on words have internal hardware which increments the byte ad dress appropriately to load the two consecutive bytes in one clock cycle To use an absolute wo...

Page 132: ...g Beginning of string at lower address String length times 8 bit data by Incrementing addresses 1 per byte in string Single word Even address if odd address is used the LSB bit of address is assumed 0...

Page 133: ...4 0x00BC AC5 0x00DE Example 4 5 5 MOV STR 4 2 MOV AP0 2 MOVS A0 0x0003 Refer to Figure 4 4 for this example The byte string length is 4 AP0 is loaded with 2 and points to AC2 The third instruction loa...

Page 134: ...In the second instruction this flag bit is placed in the TAG status bit of the STAT and the value in RAM location 0x0003 2 is placed in A0 The third instruction resets the flag tag to 0 at the same fl...

Page 135: ...x0031 into A0 and also sets the TAG bit of STAT to 1 corre sponding to the last memory location of the string which is word address 0x0032 in this case The next two instructions verify this by setting...

Page 136: ...Affects OF bit of STAT in case of overflow Fractional SFM RFM STAT FM 1 enables fractional multiplication shift mode The multiplier is shifted left 1 bit to produce a 17 bit operand This mode is used...

Page 137: ...in unsigned mode The lower 16 bits of the result is stored in A0 and the upper 16 bits are stored in PH The final result is 0x400000 where PH holds the value 0x0040 and A0 holds the lower 16 bits Noti...

Page 138: ...A0 is loaded with 0x10001000 When the two values are added together it causes an overflow The OF bit of the STAT is set to 1 the 16 bit MSBs of the string become 0x7FFF and the lower bits of the strin...

Page 139: ...count length N This immediately precedes the instruction to be repeated This next instruction is repeated N 2 times The RPT instruction is useful for clearing RAM locations filtering etc If the repeat...

Page 140: ...nterrupts if enabled before the execution of BEGLOOP will automatically be re enabled after exiting the loop Enabling interrupts inside the loop have no effect Queued interrupts are processed accordin...

Page 141: ...tus is modified representing the outcome of the entire operation Examine the following examples Table 4 43 Initial Processor State for String Instructions Registers register value AP0 2 AP1 21 0x15 AP...

Page 142: ...equence ends with ADDS or SUBS used with PH 6 These sequences may not give same result when single step debugging because single stepping changes the internal state They should be used either with a h...

Page 143: ...adrs The string length is defined in STR register MOVS An An The program memory string address is stored in accumulator An or its offset An Store the contents of this address to the accumulator strin...

Page 144: ...fficient data see section 4 10 any interrupt occurring between loading the first coefficient and the execution of a FIRK CORK will change the last value of DP if the interrupt routine uses a lookup in...

Page 145: ...he OUT instruction Class 6 The OUT instruction can specify a memory address and a 4 bit port address It can also use an accumulator or offset accumulator and a 6 bit port address String transfers are...

Page 146: ...extended accumulate cycle is added to prevent the arithmetic overflow common in auto correlation filters FIR COR Instructions The execution of the filter instructions is shown in Figure 4 6 To use FI...

Page 147: ...Second initialize filter coeffs to proper values NOTE In this code N must be less than 33 since there are only 32 accumulator registers mov STR N 2 set string length to N zacs a0 zero out N accumulato...

Page 148: ...er Thus R0 will increment by R5 after the first multiply This will become more clear after examining the next ex ample code The third detail is that the filter coefficients take up only N RAM location...

Page 149: ...pose a four word circular buffer starts at RAM location 0x0100 and ends at 0x0106 N 3 In order to wrap around from location 0x0106 back to location 0x0100 the value 0x006 must be subtracted from 0x010...

Page 150: ...ring operation in the example is located in AC0 lower word and AC1 high word This 32 bit result is stored in the SampleOut RAM location R0 should be pointing to the oldest sample The oldest sample x k...

Page 151: ...ing code rovm reset overflow mode mov R5 2 N circular buffer length 3 words mov A0 FIRK_COEFFS Loads address of lookup table mov A0 A0 Loads first coefficient to A0 and sets DP mov MR A0 Load first co...

Page 152: ...AC0 16 32 in AC1 mov A0 nextSample Replace last sample with newest sample and update mov R0 A0 the start of the mov startOfBuff R0 circular buffer to here R0 The set up for the FIRK CORK instruction...

Page 153: ...uf coeff_array ACr 1 ACr 2 ACr y For COR CORK ACr ACr 1 y For FIR FIRK TAG 1 for 2nd to last sample for Circular buffer operation Accumulators Pointer Point to accumulator ACr An ACn Circular buffer o...

Page 154: ...0 0 h 3 h 4 0 0 0 h N 1 0 0 0 h N 0 0 16 Bits 17th Bit coeff_array coeff_array is stored in program or data memory based on filter instruction x k x k 1 x k 2 0 0 0 x k 3 x k 4 0 0 0 x k N 0 0 1 x k 1...

Page 155: ...F ZF 0 CF 0 Below unsigned B NAE NB AE ZF 0 CF 1 Above unsigned A NBE NA BE ZF 1 SF 0 Greater signed G NLE NG LE ZF 1 OF 0 Equal E NE OF 1 Overflow flag OF NOF ZF 0 SF 1 Less signed L NGE NL GE RCF 1...

Page 156: ...Post modification of a register This can be either next A or Rmod and will be specified in the instruction The following table describes the meanings of the symbols used in the instruction set descri...

Page 157: ...the addressed memory and the upper bits may not be used If n is not provided data width is 16 bits cc Condition code bits used with conditional branch calls and test flag bit instructions cc Condition...

Page 158: ...gh register 16 bits PL Product low register 16 bits cannot be read written directly R Rx register treated as a general purpose register This bit is not related to any addressing mode RCF Register carr...

Page 159: ...0 0 x 0 0 Short relative 1 1 nR 2 R6 offset7 1 offset7 Relative to R5 1 1 nR 2 Rx R5 0 1 0 Rx 0 0 Long relative 2 2 nR 4 Rx offset16 0 0 1 Rx 0 0 Rx 0 0 Indirect 1 1 nR 2 Rx 0 1 Indirect 1 1 nR 2 Rx 0...

Page 160: ...the legend in Section 4 13 to help with individual instruction descriptions Each instruction is discussed in detail and provides the following information Assembler syntax Clock cycles required with...

Page 161: ...for two operands dest src src1 for three operands PC PC w Flags Affected dest is An OF SF ZF CF are set accordingly dest is Rx RCF RZF are set accordingly src1 is adrs TAG is set accordingly Opcode I...

Page 162: ...ut result in A2 Add value in R5 to R2 and store in R2 Example 4 14 1 2 ADD A1 A1 0x1221 Add immediate value of 0x1221 to A1 and store result in A1 Example 4 14 1 3 ADD A0 A0 PH Add PH to accumulator A...

Page 163: ...re set accordingly dest is Rx RCF RZF are set accordingly Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDB An imm5 1 0 1 0 0 0 0 An imm8 ADD Rx imm8 1 0 1 1 0 0 k4 k3 k2 k7 k6 k5 Rx k...

Page 164: ...this instruction An in this instruc tion should be the same as An in one of the listed class 1b instruction Offsets are allowed See Section 4 8 for more detail Execution dest string src string src1 st...

Page 165: ...n multiplies MR and A0 adds PL to A0 and stores the result in A0 The second instruction adds PH to the second word of memory string A0 and puts the result in accumulator string A0 Note that MULAPL and...

Page 166: ...a16 for direct or offset16 long relative see section 4 13 AND An An imm16 next A 1 1 1 0 0 next A An 1 0 1 0 0 1 A A x imm16 AND An An An next A 1 1 1 0 0 next A An 0 1 0 1 0 0 A A AND TFn flagadrs 1...

Page 167: ...mple 4 14 4 2 AND A0 A0 0xff0f A Predecrement accumulator pointer AP0 And immediate value 0xff0f to register accumulator A0 store result in accumulator A0 Example 4 14 4 3 AND TF2 0x0020 AND global fl...

Page 168: ...ted OF SF ZF CF are set accordingly Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ANDB An imm8 1 0 1 0 1 0 1 An imm8 Description Bitwise AND src byte and byte stored in dest register an...

Page 169: ...t16 long relative see section 4 13 ANDS An An pma16 1 1 1 0 0 1 1 An 1 0 1 0 0 1 A A x pma16 ANDS An An An 1 1 1 0 0 1 1 An 0 1 0 1 0 0 A A Description Syntax Description ANDS dest src Bitwise AND of...

Page 170: ...are actually queued until the loop is complete see ENDLOOP The loop executes N number of times Thus N 2 should be loaded in R4 in order to loop N times BEGLOOP and ENDLOOP block has following restrict...

Page 171: ...f An is in the following table An Bit 9 Bit 8 A0 0 0 A1 0 1 A2 1 0 A3 1 1 Description PC w is pushed onto the top of stack TOS and the second word operand or accumulator value is loaded into the PC Ca...

Page 172: ...ions 4 86 Note You can not RET to a RET For example the following code can cause prob lems CALL my sub RET To eliminate any problem a NOP or other code should be inserted between the CALL and the RET...

Page 173: ...CXS CXG CRA pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 pma16 label label label label label label label label label label label l...

Page 174: ...Conditional on RZF 1 Not condition RZF 0 0 1 0 1 1 RZP RNZP Conditional on value of Rx 0 Not available on calls Not condition Rx 0 0 1 1 0 0 RLZP RNLZP Conditional on MSB of Rx 1 Not available on call...

Page 175: ...all on not equal CG pma16 CNG pma16 CNLE pma16 CLE pma16 Conditional call on greater signed Conditional call on not greater signed CIN1 pma16 CNIN1 pma16 Conditional call on IN1 1 Conditional call on...

Page 176: ...onics are provided as a way of improving source code readability They generate the same opcode as the original mnemonic For example CA call above tests the same conditions as CNBE call not below or eq...

Page 177: ...0 0 An adrs x dma16 for direct or offset16 long relative see section 4 13 CMP An imm16 next A 1 1 1 0 0 next A An 0 1 1 0 0 1 A A x imm16 CMP An An next A 1 1 1 0 0 next A An 1 0 0 0 0 0 0 0 CMP An An...

Page 178: ...escriptions 4 92 Example 4 14 10 3 CMP R2 0xfe20 Compare value at R2 to immediate value 0xfe20 and change the STAT flags accordingly Example 4 14 10 4 CMP R0 R5 Compare value at R0 to R5 and change th...

Page 179: ...ccordingly src is Rx RCF RZF are set accordingly Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CMPB An imm8 1 0 1 0 0 1 1 An imm8 CMPB Rx imm8 1 0 1 1 1 1 k4 k3 k2 k7 k6 k5 Rx k1 k0 Des...

Page 180: ...r offset16 long relative see section 4 13 CMPS An pma16 1 1 1 0 0 1 1 An 0 1 1 0 0 1 A 0 x pma16 CMPS An An 1 1 1 0 0 1 1 An 1 0 0 0 0 0 0 0 CMPS An An 1 1 1 0 0 1 1 An 1 0 0 0 0 0 1 0 Description Sub...

Page 181: ...ion is detailed in section 4 11 Flags Affected none Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COR An Rx 1 1 1 0 1 0 0 An 1 1 0 Rx 1 1 Description When used with repeat will execute...

Page 182: ...detailed in section 4 11 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CORK An Rx 1 1 1 0 1 0 0 An 1 0 0 Rx 1 1 Description When used with repeat will execute 16 16...

Page 183: ...instruction marks the end of a loop defined by BEGLOOP If register R4 is not negative R4 is decremented by n and the loop is executed again beginning with the first instruction after the BEGLOOP If R...

Page 184: ...AP if mod specified new most significant word of dest STAT SF PC PC 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTSGN An next A 1 1 1 0 0 next A An 0 1 1 1 1 0...

Page 185: ...e processor to stall when an attempt is made to sign extend a string that has all zeros in it Also the same interrupt problem on the accumulator pointers exists if the instruction just before is not a...

Page 186: ...OINT TO LSW OF ACCUM STRING MOV AP1 3 Point to loc corresponding to extended word in acc ZAC A1 INITIALIZE EXTENDED SIGN VALUE as positive MOVS A0 R0 R0 POINTS TO VALUE IN MEMORY JNS POSITIVE branch a...

Page 187: ...s Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FIR An Rx 1 1 1 0 1 0 0 An 0 1 0 Rx 1 1 Description Finite impulse response FIR filter Execute finite impulse response filt...

Page 188: ...criptions 4 102 See Also RPT FIRK COR CORK Example 4 14 18 1 RPT 0 FIR A0 R0 Computes the calculation for 2 tap FIR filter with 32 bit accumulation See section 4 11 for more detail on the setup of coe...

Page 189: ...1 0 1 0 0 An 0 0 0 Rx 1 1 Description Finite impluse response FIR filter Execute finite impulse response filter taps using coefficients from program memory and samples from data memory Address refere...

Page 190: ...4 20 1 MOV A0 0 OUT 0x34 A0 Turn off DAC MOV A0 0x0400 Turn off clock idle bit 1 OUT 0x3d A0 Write in ClkSpdCtrl write only IN A0 0x38 Read IntGenCtrl register value OR A0 A0 0x4000 Set ARM 1 OUT 0x38...

Page 191: ...de Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IN adrs port4 1 1 0 0 0 port4 adrs x dma16 for direct or offset16 long relative see section 4 13 IN An port6 1 1 1 0 1 1 0 An port6 A Descripti...

Page 192: ...11 10 9 8 7 6 5 4 3 2 1 0 INS An port6 1 1 1 0 1 1 1 An port6 0 A Description Input string from same port port6 to accumulator string Strings can be input to accumulators from one of 64 port addresse...

Page 193: ...1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTD 1 1 1 1 1 1 1 1 0 1 0 0 1 0 0 0 0 Description Disables interrupts Resets bit 4 the IM interrupt mask bit of stat...

Page 194: ...is STAT bit 4 PC PC 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTE 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 Description Enables interrupts Sets bit 4 the IM interrup...

Page 195: ...N R 5 Execution PC TOS R7 R7 2 TOS R7 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IRET 1 1 0 1 1 1 1 0 1 0 1 1 1 1 1 1 0 See Also RET CALL Ccc INTE INTD Descripti...

Page 196: ...pma16 Rmod pma16 Rmod pma16 Rmod pma16 Rmod pma16 Rmod label label label label label label label label label label label label label label label label label label label label label label JNZ JNS JC JN...

Page 197: ...NO Conditional if OF 1 Not condition OF 0 0 1 0 0 0 RC RNC Conditional on RCF 1 Not condition RCF 0 0 1 0 0 1 RA RNA Conditional on RZF 0 and RCF 1 Not condition RZF 0 or RCF 1 0 1 0 1 0 RE RNE Condit...

Page 198: ...not equal JG pma16 Rmod JNLE Conditional jump on greater signed JNG pma16 Rmod JLE Conditional jump on not greater signed JIN1 pma16 Rmod Conditional jump on port D pin PD0 1 JNIN1 pma16 Rmod Conditio...

Page 199: ...onal jump on transfer ZF 1 zero JXNZ pma16 Rmod Conditional jump on transfer ZF 0 not equal JZ pma16 Rmod Conditional jump on ZF 1 JNZ pma16 Rmod Conditional jump on ZF 0 Alternate mnemonics are provi...

Page 200: ...0 1 0 1 0 0 0 0 0 x pma16 JMP pma16 Rx 1 0 0 0 0 0 0 1 0 1 0 1 Rx 0 1 x pma16 JMP pma16 Rx 1 0 0 0 0 0 0 1 0 1 0 1 Rx 1 0 x pma16 JMP pma16 Rx R5 1 0 0 0 0 0 0 1 0 1 0 1 Rx 1 1 x pma16 JMP An 1 0 0 0...

Page 201: ...ext A 1 1 nR 3 3 MOV adrs Rx Table 4 46 Table 4 46 4a MOV Rx adrs Table 4 46 Table 4 46 4a MOV Rx imm16 2 2 N R 4c MOV Rx R5 1 1 nR 3 4d MOV SV adrs 4 1 1 nR 3 5 MOV PH adrs Table 4 46 Table 4 46 5 MO...

Page 202: ...0 1 0 A next A An adrs x dma16 for direct or offset16 long relative see section 4 13 MOV adrs An 0 1 0 1 1 1 0 An adrs x dma16 for direct or offset16 long relative see section 4 13 MOV An imm16 next A...

Page 203: ...ect or offset16 long relative see section 4 13 MOV adrs MR 1 1 0 1 0 1 0 0 0 adrs x dma16 for direct or offset16 long relative see section 4 13 MOV adrs STAT 1 1 0 1 0 0 0 1 0 adrs x dma16 for direct...

Page 204: ...er MOV MR adrs Move data memory word to MR set multiplier signed mode MOV adrs An Move ROM word at An to data memory MOV APn adrs Move data memory word lower 6 bits to APn register MOV STAT adrs Move...

Page 205: ...ion 0x0200 Example 4 14 28 3 MOV 0x0200 2 A1 Transfer content of program memory location pointed by A1 to word data memory location 0x0200 Example 4 14 28 4 MOV A2 0xf200 A Predecrement accumulator po...

Page 206: ...stored in R3 to accumulator pointer AP2 Example 4 14 28 18 MOV R6 8 2 DP Copy data pointer DP to data memory word location pointed by R6 offset by 8 location short relative addressing Example 4 14 28...

Page 207: ...re set accordingly Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOVAPH An MR adrs 0 1 1 0 1 0 0 An adrs x dma16 for direct or offset16 long relative see section 4 13 Description Move R...

Page 208: ...n MR adrs 0 1 1 0 1 0 1 An adrs x dma16 for direct or offset16 long relative see section 4 13 Description Move RAM word to MR add PH to second word in An string Certain restriction applies to the use...

Page 209: ...1 0 MOVB An adrs 0 1 0 0 1 1 0 An adrs x dma16 for direct or offset16 long relative see section 4 13 MOVB adrs An 0 1 0 1 0 0 0 An adrs x dma16 for direct or offset16 long relative see section 4 13 MO...

Page 210: ...its of accumulator A0 to the data memory byte pointed by R2 Example 4 14 29 3 MOVB A0 0xf2 Load accumulator A0 with value of 0xf2 Example 4 14 29 4 MOVB MR 34 Load MR register with immidiate value of...

Page 211: ...6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOVBS An adrs 8 0 1 0 0 1 1 1 An adrs x dma16 for direct or offset16 long relative see section 4 13 MOVBS adrs 8 An 0 1 0 1 0 0 0 An adrs x dma16 for direct or...

Page 212: ...are set accordingly dest is adrs XSF XZF are set accordingly src is adrs TAG bit is set accordingly Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOVS An adrs 0 0 1 0 A 1 1 An adrs x dm...

Page 213: ...shift operation as if the sequence was a single string MOVS An An Move program memory string at An to An See Also MOVU MOV MOVT MOVB MOVBS Example 4 14 31 1 MOVS A2 R6 Load the string pointed by R6 to...

Page 214: ...cordingly Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOVSPH An MR adrs 0 1 1 0 0 1 0 An adrs x dma16 for direct or offset16 long relative see section 4 13 Description Move data memor...

Page 215: ...0 MOVSPHS An MR adrs 0 1 1 0 0 1 1 An adrs x dma16 for direct or offset16 long relative see section 4 13 Description Move data memory word string to MR subtract PH from second word An string Store re...

Page 216: ...lags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MOVT adrs TFn 1 1 0 1 0 1 1 1 fig adrs x dma16 for direct or offset16 long relative see section 4 13 Description Move TF...

Page 217: ...An next A 1 1 1 0 0 next A An 1 0 1 1 1 0 A 0 MOVU MR adrs 1 1 0 1 1 1 0 0 1 adrs x dma16 for direct or offset16 long relative see section 4 13 Description Copy value of src to dest Premodification o...

Page 218: ...ure 4 8 Valid Moves Transfer in MSP50P614 MSP50C614 Instruction Set PH An Rx APn STR MR SV Immediate B B B S B S S B ROM RAM S I O xxxxxx xxxx00 STAT TOS B Flag Bit NOTE B Byte move possible S String...

Page 219: ...Multiply MR and src The 16 MSBs of the 32 bit product are stored in the the PH register The contents of the accumulator are not changed The upper 16 bits of the result are rounded for MUL An but not...

Page 220: ...1 1 1 0 1 0 adrs x dma16 for direct or offset16 long relative see Section 4 13 Description Perform multiplication of multiply register MR and effective data memory value add 08x00 to the product The...

Page 221: ...4 3 2 1 0 MULS An 1 1 1 0 0 1 1 An 1 1 1 1 0 0 A 0 Description Multiply MR and the value in src The 16 MSBs of the ns 3 x 16 bit product are stored in the PH register The value in src is unchanged and...

Page 222: ...n of multiply register MR and value of src The 16 MSBs of the 32 bit product are stored in the product high PH register The 16 LSBs of the product contained in product low PL register added to dest Ce...

Page 223: ...1 1 0 0 1 0 A A Description Perform multiplication of multiply register MR and value of src The 16 MSBs of the ns 3 16 bit product are stored in the product high PH register The 16 LSBs of the produc...

Page 224: ...gister MR and value of src The 16 MSBs of the 32 bit product are stored in the product high PH register The 16 LSBs of the product contained in product low PL register are subtracted from dest Certain...

Page 225: ...1 An 1 1 0 0 0 0 A A Description Perform multiplication of multiply register MR and value of src The 16 MSBs of the ns 3 16 bit product are stored in the product high PH register The 16 LSBs of the pr...

Page 226: ...0 1 1 0 A A Description Perform multiplication of multiply register MR and value of src The 16 MSBs of the 32 bit product are stored in the product high PH register The 16 LSBs of the product containe...

Page 227: ...n 4 13 MULSPL S An An 1 1 1 0 0 1 1 An 1 1 0 1 1 0 A A Description Perform multiplication of multiply register MR and value of src string The 16 MSBs of the ns 3 16 bit product are stored in the produ...

Page 228: ...1 Flags Affected OF SF ZF CF are set accordingly Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NEGAC An An next A 1 1 1 0 0 next A An 0 0 0 0 0 0 A A Description Perform two s compleme...

Page 229: ...src PC PC 1 Flags Affected OF SF ZF CF are set accordingly Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MULSPL S An An 1 1 1 0 0 1 1 An 0 0 0 0 0 0 A A Description Perform two s comple...

Page 230: ...3 9d Execution PC PC 1 No operation Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOP 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Description This instruction performs no ope...

Page 231: ...d OF SF ZF CF are set accordingly Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOTAC An An next A 1 1 1 0 0 next A An 0 0 0 0 1 0 A A Description Premodify accumulator pointer if speci...

Page 232: ...ZF CF are set accordingly Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOTACS An An 1 1 1 0 0 1 1 An 0 0 0 0 1 0 A A Description Perform one s complement of src accumulator string and...

Page 233: ...a16 for direct or offset16 long relative see section 4 13 OR An An imm16 next A 1 1 1 0 0 next A An 1 0 0 0 0 1 A A OR An An An next A 1 1 1 0 0 next A An 0 1 0 0 1 0 A A OR TFn flagadrs 1 0 0 1 1 fig...

Page 234: ...OR A1 A1 A1 A Pre decrement accumulator pointer AP1 OR accumulator A1 to accumulator A1 put result in A1 Example 4 14 52 4 OR TF1 R6 0x22 OR TF1 bit in STAT with tag bit 17th bit at relative flag addr...

Page 235: ...dest OR src PC PC 1 Flags Affected OF SF ZF CF are set accordingly Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ORB An imm8 1 0 1 0 1 0 0 An imm8 Description Bitwise OR byte of src and...

Page 236: ...1 0 A A Description Bitwise OR of src and dest Result is stored in dest If three operands are specified then logical OR src1 and src store result in dest Syntax Description ORS An adrs OR RAM string...

Page 237: ...adrs 1 1 0 0 1 port4 adrs x dma16 for direct or offset16 long relative see section 4 13 OUT port6 An 1 1 1 0 1 1 0 An port6 1 A Description Output to I O port Words 16 bits in memory can be output to...

Page 238: ...0 9 8 7 6 5 4 3 2 1 0 OUTS port6 An 1 1 1 0 1 1 1 An port6 1 A Description Output to I O port Word in the accumulator string can be output to one of 64 port addresses String operation writes several c...

Page 239: ...ion Return from call or vectored call Pop stack to program counter continue execution Returns from subroutine calls CALL Ccc instructions and interrupts are different because of the way each process i...

Page 240: ...two groups of memory flag addresses global flags which are the first 64 word locations in RAM and relative flags which are 64 locations relative to the page register R6 Flag address flagadrs only add...

Page 241: ...xecution STAT FM 0 PC PC 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFM 1 1 1 1 1 1 1 1 0 1 1 0 1 0 0 0 0 Description Resets fractional mode Clears bit 3 in sta...

Page 242: ...1 N R 9d Execution STAT OM 0 PC PC 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFM 1 1 1 1 1 1 1 1 0 1 1 0 1 0 0 0 0 Description Resets overflow mode in status r...

Page 243: ...xecution completes Syntax Description RPT adrs 8 Load data memory byte to repeat counter repeat next instruction RPT imm8 Load immediate byte to repeat counter repeat next instruction See Also BEGLOOP...

Page 244: ...addressing modes are available Note that this instruction accesses only the 17th bit of the RAM location For odd RAM byte addresses the least significant bit is ignored See Also STAG RFLAG SFLAG Examp...

Page 245: ...clk Class RXM 1 1 N R 9d Execution STAT XM 0 PC PC 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXM 1 1 1 1 1 1 1 1 0 1 0 1 1 0 0 0 0 Description Reset extended...

Page 246: ...flagadrs 1 0 0 1 1 1 0 1 0 1 flagadrs Description Set flag at addressed memory location flagadrs includes two groups of memory flag adrresses global flags which are the first 64 words in RAM and relat...

Page 247: ...ss SFM 1 1 N R 9d Execution STAT FM 1 PC PC 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXM 1 1 1 1 1 1 1 1 0 1 1 0 0 0 0 0 0 Description Sets bit 3 the FM bit i...

Page 248: ...y the SV register into a 32 bit result This result is zero filled or sign extended on the left based on the setting of the extended sign mode XM bit in the status register The upper 16 bits are latche...

Page 249: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 SHLAC An An next A 1 1 1 0 0 next A An 0 0 1 1 0 0 A A Description Premodify accumulator pointer if specified Shift source accumulator src or its offset left by one bi...

Page 250: ...2 1 0 SHLACS An An 1 1 1 0 0 1 1 An 0 0 1 1 0 0 A A Description Shift the source accumulator string src or its offset left one bit and store the result in destination accumulator string or its offset...

Page 251: ...16 bits are latched into the product high PH register The lower 16 bits of the result product low PL register is added to the destination accumulator or its offset This instruction propagates the shif...

Page 252: ...product low PL register are added to the destination accumulator or its offset This instruction propagates the shifted bits to the next accumulators in the string Syntax Description SHLAPLS An adrs Sh...

Page 253: ...cumulator string value left nSV bits as specified by the SV register into a nS 2 x 16 bit result The result is zero filled or sign extended on the left based on the setting of the extended sign mode X...

Page 254: ...d into the product high PH register The lower 16 bits of the result product low PL register is subtracted from the destination accumulator or its offset This instruction propagates the shifted bit to...

Page 255: ...r its offset This instruction propagates the shifted bit to the next accumulator Syntax Description SHLSPLS An adrs Shift RAM string left subtract PL from An SHLSPLS An An Shift An string left subtrac...

Page 256: ...16 bits are latched into the PH register The lower 16 bits of the result PL are transferred to the destination accumulator or its offset This instruction propagates the shifted bit into PH Syntax Desc...

Page 257: ...us register The upper 16 bits are latched into the PH register The result is transferred to the destination accumulator or its offset This instruction propagates the shifted bits to the next accumulat...

Page 258: ...An An next a 1 1 1 0 0 next A An 0 1 0 1 1 0 A A Description Premodify accumulator pointer if specified Shift source accumulator src or its offset to right one bit and store the result into dest accu...

Page 259: ...cumulator string right one bit and store the result into An string MSB of each accumulator in the result will be set according to extended sign mode XM bit in the status register This instruction shif...

Page 260: ...ion STAT OM 1 PC PC 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOVM 1 1 1 1 1 1 1 1 0 1 1 0 1 0 0 0 0 Description Sets overflow mode in status register STAT bit...

Page 261: ...ve see section 4 13 Description Sets the tag bit at the addressed memory location All addressing modes are available Note that this instruction accesses only the 17th bit of the RAM location The argum...

Page 262: ...3 2 1 0 SUB An An adrs next A 0 0 0 0 A next A An adrs x dma16 for direct or offset16 long relative see section 4 13 SUB An An imm16 next A 1 1 1 0 0 next A An 0 1 0 0 0 1 A A SUB An An PH next A 1 1...

Page 263: ...Subtract R5 from Rx See Also SUBB SUBS ADD ADDB ADDS Example 4 14 80 1 SUB A1 A1 74 Subtract 74 decimal immediate from accumulator A1 put result in accumulator A1 Example 4 14 80 2 SUB A0 A0 2 A Pre i...

Page 264: ...BB An imm8 1 0 1 0 0 1 0 An imm8 SUBB Rx imm8 1 0 1 1 0 1 k4 k3 k2 k7 k6 k5 Rx k1 k0 Description Subtract value of src byte from value of dest byte and store result in dest Note that subtraction is pe...

Page 265: ...n one of the listed class 1b instruc tion Offsets are allowed See Section 4 8 for detail Execution premodify AP if mod specified dest dest src for two operands dest src src1 for three operands PC PC w...

Page 266: ...is maintained i e PH is subtracted from the second word of the string Also only the second word is copied to the destination string Example 4 14 82 1 SUBS A0 A0 R2 Subtract data memory string beginni...

Page 267: ...Class SXM 1 1 N R 9d Execution STAT XM 1 PC PC 1 Flags Affected None Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SXM 1 1 1 1 1 1 1 1 0 1 0 1 0 0 0 0 0 Description Sets extended sign m...

Page 268: ...ed call Macro call Push next address onto stack load PC with the content of the address obtained by adding vector8 to 0x7F00 The execution of the instruction continues from the new PC location RET ins...

Page 269: ...relative see section 4 13 XOR An An imm16 next A 1 1 1 0 0 next A An 1 1 0 0 0 1 A A XOR An An An next A 1 1 1 0 0 next A An 0 1 0 0 0 0 A A XOR TFn flagadrs 1 0 0 1 1 fig Not 1 1 0 flagadrs XOR TFn...

Page 270: ...mode after the operation Example 4 14 85 5 XOR A2 A2 R2 R5 A Pre decrement pointer AP2 XOR word at effective address R2 R5 to new accumulator A2 put result in accumulator A2 Value of R2 is not modifie...

Page 271: ...Affected dest is An OF SF ZF CF are set accordingly Opcode Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XORB An imm8 0 0 1 0 1 1 0 An imm8 Description Bitwise logical XOR lower 8 bits of An a...

Page 272: ...are specified then logical XOR src string and src1 string store result in dest string Syntax Description XORS An adrs XOR data memory string to An string XORS An An pma16 XOR program memory string to...

Page 273: ...dest 0 PC PC 1 Flags Affected ZF 1 Instructions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ZAC An next A 1 1 1 0 0 next A An 0 0 0 1 1 0 0 A Description Zero the specified accumulator Preincrement or p...

Page 274: ...ions 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ZACS An 1 1 1 0 0 1 1 An 0 0 0 1 1 0 0 A Description Zero the specified accumulator string See Also ZAC Example 4 14 89 1 ZACS A1 Reset the content of off...

Page 275: ...offset16 long relative see section 4 13 ADDS An An pma16 1 1 1 0 0 1 1 An 0 0 0 0 0 1 A A x pma16 ADDS An An An 1 1 1 0 0 1 1 An 0 0 1 0 1 0 A A ADDS An An PH 1 1 1 0 0 1 1 An 0 1 1 0 1 0 A A AND An...

Page 276: ...An 0 1 1 0 0 1 A 0 x pma16 CMPS An An 1 1 1 0 0 1 1 An 1 0 0 0 0 0 0 0 CMPS An An 1 1 1 0 0 1 1 An 1 0 0 0 0 0 1 0 COR An Rx 1 1 1 0 1 0 0 An 1 1 0 Rx 1 1 CORK An Rx 1 1 1 0 1 0 0 An 1 0 0 Rx 1 1 END...

Page 277: ...g relative see section 4 13 MOV An imm16 next A 1 1 1 0 0 next A An 0 0 1 0 0 1 0 A MOV MR imm16 next A 1 1 1 0 0 next A An 1 1 1 0 0 1 0 0 MOV An An next A 1 1 1 0 0 next A An 0 0 1 1 1 0 A A MOV An...

Page 278: ...offset16 long relative see section 4 13 MOV adrs STR 1 1 0 1 0 0 0 1 1 adrs x dma16 for direct or offset16 long relative see section 4 13 MOV adrs DP 1 1 0 1 0 1 0 1 0 adrs x dma16 for direct or offs...

Page 279: ...6 1 1 1 0 0 1 1 An 0 0 1 0 0 1 A A MOVS PH An 1 1 1 0 0 1 1 An 1 0 1 0 1 0 A 0 MOVS SV An 1 1 1 0 0 1 1 An 1 0 1 0 0 0 A 0 MOVS An PH 1 1 1 0 0 1 1 An 0 1 1 1 0 0 A A MOVS An An 1 1 1 0 0 1 1 An 0 0 1...

Page 280: ...relative see section 4 13 MULSPLS An An 1 1 1 0 0 1 1 An 1 1 0 0 0 0 A A MULTPL An adrs 0 1 1 0 0 0 0 An adrs x dma16 for direct or offset16 long relative see section 4 13 MULTPL An An next A 1 1 1 0...

Page 281: ...0 0 0 0 0 0 SHL An next A 1 1 1 0 0 next A An 1 1 1 1 1 0 A 0 SHLS An 1 1 1 0 0 1 1 An 1 1 1 1 1 0 A 0 SHLAPL An adrs 0 1 1 1 1 0 0 An adrs x dma16 for direct or offset16 long relative see section 4 1...

Page 282: ...1 Rx 0 0 SUB Rx R5 1 1 1 1 1 1 1 0 0 1 0 1 Rx 0 0 SUBB An imm8 1 0 1 0 0 1 0 An imm8 SUBB Rx imm8 1 0 1 1 0 1 k4 k3 k2 k7 k6 k5 Rx k1 k0 SUBS An An adrs 0 0 0 1 A 1 1 An adrs x dma16 for direct or of...

Page 283: ...RA RNA Conditional on RZF 0 and RCF 1 Not condition RZF 0 or RCF 1 0 1 0 1 0 RE RNE Conditional on RZF 1 Not condition RZF 0 0 1 0 1 1 RZP RNZP Conditional on value of Rx 0 Not available on Calls Not...

Page 284: ...nR 3 3 ADD Rx imm16 2 2 N R 4c ADD Rx R5 1 1 nR 3 4d ADD APn imm5 1 1 N R 9c ADDB An imm8 1 1 N R 2a ADDB Rx imm8 1 1 N R 4b ADDS An An adrs Table 4 46 Table 4 46 Table 4 46 1a ADDS An An pma16 nS 4 2...

Page 285: ...ma16 nS 4 2 N R 2b CMPS CMPS An An An An nS 3 1 nR 3 3 COR An Rx 3 1 3 nR 2 9a CORK An Rx 3 1 3 nR 2 9a ENDLOOP n 1 1 N R 9d EXTSGN An next A 1 1 nR 3 3 EXTSGNS An nS 3 1 nR 3 3 FIR An Rx 2 1 2 nR 2 9...

Page 286: ...MR An next A 1 1 nR 3 3 MOV adrs Rx Table 4 46 Table 4 46 4a MOV Rx adrs Table 4 46 Table 4 46 4a MOV Rx imm16 2 2 N R 4c MOV Rx R5 1 1 nR 3 4d MOV SV imm4 1 1 N R 5 MOV SV adrs 1 1 nR 3 5 MOV PH adr...

Page 287: ...4 46 Table 4 46 1b MOVB adrs An Table 4 46 Table 4 46 1b MOVB An imm8 1 1 N R 2a MOVB MR imm8 1 1 N R 2a MOVB Rx imm8 1 1 N R 4b MOVBS An adrs Table 4 46 Table 4 46 1b MOVBS adrs 8 An Table 4 46 Table...

Page 288: ...ble 4 46 Table 4 46 1b MULAPL An An next A 1 1 nR 3 3 MULAPLS An adrs Table 4 46 Table 4 46 1b MULAPLS An An nS 3 1 nR 3 3 MULSPL An adrs Table 4 46 Table 4 46 1b MULSPL An An next A 1 1 nR 3 3 MULSPL...

Page 289: ...RPT imm8 1 1 N R 9b RET 1 1 N R 5 RFLAG flagadrs 1 1 nR 3 8a RFM 1 1 nR 3 9d ROVM 1 1 N R 9d RTAG adrs Table 4 46 Table 4 46 5 RXM 1 1 N R 9d SFLAG flagadrs 1 1 nR 3 8a SFM 1 1 N R 9d SHL An next A 1...

Page 290: ...n imm16 next A 2 2 N R 2b SUB An An PH next A 1 1 nR 3 3 SUB An An An next A 1 1 nR 3 3 SUB An An An next A 1 1 nR 3 3 SUB Rx imm16 2 2 N R 4c SUB Rx R5 1 1 nR 3 4d SUBB An imm8 1 1 N R 2a SUBB Rx imm...

Page 291: ...Not condition ZF 1 or OF 0 O NO Conditional if OF 1 Not condition OF 0 RC RNC Conditional on RCF 1 Not condition RCF 0 RA RNA Conditional on RZF 0 and RCF 1 Not condition RZF 0 or RCF 1 RE RNE Condit...

Page 292: ...1 PDx high input states bidirectional PD4 inverting and PD5 positive comparator inputs if CE 1 in IO 0x38 PD4 triggers INT6 PD5 triggers INT7 PD2 triggers INT3 PD3 triggers INT4 0x1C 8 Port D Control...

Page 293: ...M clock E1 Timer1 enable D4 D5 g g PD4 rising edge interrupt PD5 falling edge interrupt 0 1 MC MC E2 Timer2 enable D5 PD5 falling edge interrupt 1 MC 0 disable 1 enable 0x39 8 Interrupt Flag R W D5 D4...

Page 294: ...reference ClkSpdCtrl Output Number of Number of IntGenCtrl ClkSpdCtrl PLLM Master Clock PDM CPU Clock Output Sampling Number of Instructs Number of Instructs DAC P i i PDMCD Bi Over Sampling F Regist...

Page 295: ...M 10 24 k 128 128 2x 0x 26 5 11 M 5 11 M 2 56 M 19 97 k 128 256 4x 0x 4D 10 22 M 10 22 M 5 11 M 39 94 k 128 512 8x 0x 9B 20 45 M 20 45 M 10 22 M 79 87 k 128 1024 0 1x 0x 26 5 11 M 2 56 M 2 56 M 9 98 k...

Page 296: ...Instruction Set Summay 4 210 Assembly Language Instructions...

Page 297: ...grams A reduced function C compiler called C is also part of the code development tool Topic Page 5 1 Introduction 5 2 5 2 MSP50C6xx Development Tools Guidelines 5 4 5 3 MSP50C6xx Code Development Too...

Page 298: ...to another device while erasing previous devices This cycle of programming debugging and erasing typically requires several devices to be in the eraser at any time so 10 15 devices may be required to...

Page 299: ...nts If the production boards use chip on board COB be sure to bond out the scanport signals It would also be helpful to layout the board so that a 1 k resistor could be added in series with the reset...

Page 300: ...linking and debugging code for the MSP50C6xx devices Speech editing tools These are the hardware and software tools for analyzing speech files editing speech data and generating coded speech 5 2 1 1 C...

Page 301: ...J Software H SDS 6000 speech editing software 5 2 2 Tools Definitions 5 2 2 1 Hardware Tools Definitions Note All the following TI part numbers can be purchased through authorized TI distributors see...

Page 302: ...e personality card for the SPEECH EVM that has a 64 pin QFP socket for a catalog MSP50C604 and a 16 pin DIP socket for a catalog MSP53C39x see the following note This board can be used to develop host...

Page 303: ...re EMUC6xx The PC based software is used for MSP50C6xx code development and requires Microsoft Windows 95 or 98 operating systems It is one part of the MSP50C6xx code development tools along with the...

Page 304: ...rs in developing code for MSP50C6xx devices are available SDS6000 Speech Editing Tool manual Schematics Reference designs schematics for the daughter cards Schematics of the SPEECH EVM and the EVA50C6...

Page 305: ...VA50C605 supports following speaker drive op tions LM386 with volume control H bridge Direct drive If you choose LM386 or H bridge as the speaker drive option you have to use a 8 speaker If you choose...

Page 306: ...on to turn on the board If the power is provided externally from TB1 connector you have to slide the switch to the EXT position to turn on the board Step 8 Open EMU50C6xx software The yellow light on...

Page 307: ...tives use expressions and symbols These are explained below expression can be any numeric value Addition subtraction and multiplication are allowed Examples 128 2 2 220 5 2 0x200 equates to 0xAE 0x200...

Page 308: ...tions For example ADD A0 A0 1 2 adds a 1 to A0 because the argument is read as 1 2 1 but writing the argument as 1 2 may or may not give the correct result Outside parenthesis are not allowed in instr...

Page 309: ...o other things here ENDIF IFDEF symbol Start of a conditional assembly structure If the symbol has been defined either with a DEFINE directive or an EQU directive then the lines following this directi...

Page 310: ...ntroduces one or more data items of BYTE size 8 bits The bytes are placed in program memory in the order in which they are declared CHIP_TYPE chip_name This directive is provided for compatibility wit...

Page 311: ...he GLOBAL_VAR directive GLOBAL_VAR symbol symbol This directive allows a RAM variable to be referenced from another file GLOBAL_VAR should be used prior to defining a RAM variable with the RESW direct...

Page 312: ...me name with extension opt It also generates a file with extension glb where global variable initialization is taken care of if the routine main was encountered in the current file A file with extensi...

Page 313: ...ram ROM A good use of it would be for a sine table for example The syntax is simple for example constant int array 10 1 2 3 4 5 6 7 8 9 10 dummy 4 will create a series of DATA statements in the assemb...

Page 314: ...directive With Arguments The macro name must be immediately followed by a pair of parenthesis which introduces the arguments This is completely compatible with the usual C definition Example define m...

Page 315: ...ts conditional assembly if token following it has been defined not been defined by a define directive These directives are terminated by a endif directive and can be coupled with a else directive as i...

Page 316: ...tring int result int str1 int lg cmm_func copy_string int output int input int lg cmm_func rshift_string int output int input int rshift int lg ifdef _CMM cmm_func strcpy char outstring char instring...

Page 317: ...unc A library of regular C functions to substitute for the special MSP50C6xx functions is supplied with the C compiler allowing the user to compare the results of regular C programs with those of C pr...

Page 318: ...str1 and str2 of length lg 2 and puts the result in string result xor_string int result int str1 int str2 int lg exclusive ors strings str1 and str2 of length lg 2 and puts the result in string result...

Page 319: ...lgr is not at least equal to lgr 1 5 5 10 Constant Functions The only two constant functions implemented in C are xfer_const and xfer_single cmm_func xfer_const int out int constant_in int lg It tran...

Page 320: ...ers a and b to be compared are in A0 and A0 CMP A0 A0 A0 contains a A0 contains b A0 A0 ACO AZ ANEG 5 0 1 0 0 5 1 1 0 0 0 5 0 0 1 1 5 0 0 1 0 0 1 1 0 5 5 1 1 0 FFFF 0 1 0 1 0 FFFF 0 0 0 FFFF FFFF 1 1...

Page 321: ...nctions return their results via A0 but there is no guarantee that the absolute value of the A0 pointer is not changed by the function To compare integers a and b after loading a in A0 and b in A0 do...

Page 322: ...stack pointer and yet another register for BP REG_BP R5 because of its special arithmetic capabilities Before a function is called the arguments are pushed on the stack first argument first The funct...

Page 323: ...address to TOS register on RET 1 next PC TOS 2 transfer R7 to TOS 3 decrement R7 We can freely manipulate R7 before a CALL Ccc and after a RET to load and unload arguments to and from the stack The TO...

Page 324: ...m1 of length lgm1 2 by string m2 of length lgm2 2 and puts the result into string p of length lgp 2 int sign i j int mm1 mm2 pp sign 1 mm1 calloc sizeof int lgm1 2 mm2 calloc sizeof int lgm2 2 pp call...

Page 325: ...eral important considerations when using the C compiler The ram allocation must be coordinated so that a location isn t accidentally used twice In assembly this is usually done with IRX files by makin...

Page 326: ...ory used for assembly vari ables the C variables that the user defines are allocated in unused memory It can be set by building the project and finding the location of the last assembly variable This...

Page 327: ...Implementation Details 5 31 Code Development Tools R7 Param 2 Param 2 R7 Param 1 Param 1 Param 1 Param 1 R7 R5 Stack data R5 Stack data R5 Stack data Before call Parameter 1 Parameter 2...

Page 328: ...R5 C function call R7 Return Addr Return Addr Return Addr Return Addr Return Addr Return Addr Param 2 Param 2 Param 2 Param 2 Param 2 Param 2 Param 1 Param 1 Param 1 Param 1 Param 1 Param 1 R5 Stack d...

Page 329: ...old R5 old R5 old R5 old R5 old R5 old R5 Return Addr R7 Return Addr Return Addr Return Addr Return Addr Return Addr Param 2 Param 2 R7 Param 2 Param 2 Param 2 Param 2 Param 1 Param 1 Param 1 Param 1...

Page 330: ...Implementation Details 5 34 old R5 old R5 Return Addr Return Addr Param 2 Param 2 Param 1 Param 1 R7 R5 Stack data SUBB R7 4...

Page 331: ...lopment Tools C to ASM function call The stack is shown after the operation on the bottom is performed R7 Param 2 Param 2 R7 Param 1 Param 1 Param 1 Param 1 R7 R5 Stack data R5 Stack data R5 Stack dat...

Page 332: ...Implementation Details 5 36 R7 Return Addr Return Addr Param 2 Param 2 Param 1 Param 1 R5 Stack data Function call...

Page 333: ...Assembly routines are needed to support C function calls for operations such as reading writing ports and speaking The assembly code produced by the C compiler is not optimized and will not be as eff...

Page 334: ...for global variables is allocated at compile time Space for local variables is allocated on the stack at run time This means that the compiler will not generate a warning if local variables exceed th...

Page 335: ...cts The first one is a minimal implementation It does not have support for speech LCD key scanning or setting the time It offers minimum functionality to keep the number of files small It is meant to...

Page 336: ...sed in main cmm main_ram irx Allocates RAM for ISRs and mainasm asm vroncof2 asm Assembly routines for built in C functions and ISR vector table rtc rpj Project file generated by MSP50C6xx development...

Page 337: ...ssed and for saving and restoring registers in the Timer2 ISR MAIN_RAM IRX Start of memory for MAIN module is defined in include ram ram irx Timer 2 interrupt variables save_tim2_stat equ RAMSTART_CUS...

Page 338: ...isr data timer2_isr this is the timer2 isr data pd2 data pd3 data portF data pd4 data pd5 aorg 0x7ffe data 0x1ffff ROM protection word 0x7ffe data init614 reset address 0x7fff Notice that timer2 was...

Page 339: ...nd a0 TIM2ENABLE clear bit 11 TIM2 enable out IntGenCtrl a0 mov a0 32768 1 setup a 250ms period out TIM2 a0 load TIM2 and PRD2 in one step in a0 IntGenCtrl or a0 TIM2IMR TIM2ENABLE set bit 2 TIM2 inte...

Page 340: ...td instruction Because of pipeline latency interrupts can still fire for two clock cycles after an intd instruction The rpt temporarily disables interrupts and ensures that an interrupt does not fire...

Page 341: ...ssed while seconds 59 seconds seconds 60 minutes if minutes 59 minutes 0 hours if hours 12 if ampm 0 ampm 1 else ampm 0 days if days 6 days 0 end days if hours 12 hours 1 end hours end minutes end sec...

Page 342: ...g called from C instead of assembly The second one is the function in cmm1 asm for reading the value of seconds_passed Global variables are defined next An integer is used to keep track of each elemen...

Page 343: ...vroncof2 asm J rtc rpj J dsp H celp celp irx celp4 obj H common util obj util2 obj H general dsp_var irx dsputil asm getbits asm speak asm speak irx spk_ram irx H melp melp irx melp obj J modules H g...

Page 344: ...its asm Routines for requesting speech data speak asm Routines for speaking a phrase speak irx Combines irx files for each synthesis algorithm speak_ram irx Allocates RAM for speech synthesis melp Dir...

Page 345: ...5 include cmm1_ram irx End of RAM RAMEND_CUSTOMER equ RAMEND_CMM1 RAMLENGTH_CUSTOMER equ RAMEND_CUSTOMER RAMSTART_CUSTOMER The new variables csave_r3 and csave_r5 were added by using the mnemonic for...

Page 346: ...mpm qfm Include statements were used to add speech files for all of the phrases that the clock will need to say _sleepQuarterSec mov a0 8192 1 setup a 250ms period out TIM1 a0 load TIM1 and PRD1 mov a...

Page 347: ...he configuration of Timer 2 The high level program main cmm was then modified to utilize the new functionality cmm_func main goasm run any assembly stuff that needs to be run while 1 infinite loop if...

Page 348: ...te the use of C arrays This is not the clearest or easiest way to keep track of the time It was added as an example of C arrays Multidimensional arrays are not supported in C but the same functionalit...

Page 349: ...odules H general init asm io_ports irx sleep asm H isr tim2_isr asm dac_isr asm tim1_isr asm H lcd lcd asm lcd irx lcd_ram irx J speech H celp ampm qfm days qfm ones qfm teens qfm tens qfm H melp ampm...

Page 350: ...ialize the LCD before it is used set up the LCD call lcd_setio call lcd_init In cmm1 asm simple routines for writing characters and numbers were added along with routines to bring the cursor to the be...

Page 351: ...1 writeCharacter T writeCharacter U writeCharacter E break case 2 writeCharacter W writeCharacter E writeCharacter D break case 3 writeCharacter T writeCharacter H writeCharacter U break case 4 writeC...

Page 352: ...wOne for temp 0 temp 16 temp writeCharacter writeCharacter o writeCharacter break case 3 writeCharacter writeCharacter rowOne for temp 0 temp 15 temp writeCharacter writeCharacter o writeCharacter wri...

Page 353: ...e SUBB and MOV instruction If interrupts do happen between SUBB and MOV instructions the parameter in the stack is corrupted by the return address pushed by the hardware This problem may not be easily...

Page 354: ...is in a low power mode Hardware breakpoints should not be placed within two cycles of a label accessed with a CALL instruction or as an ISR This results in unreliable performance of the breakpoint Th...

Page 355: ...n on application circuits processor initialization sequence resistor trim setting synthesis code memory overlays and ROM usage Topic Page 6 1 Application Circuits 6 2 6 2 Initializing the MSP50C6xx 6...

Page 356: ...ross VDD and VPP may be omitted shorted if the application does not require use of the scan port interface The same applies for the 1 k resistor which appears at the RESET pin the resistor may be shor...

Page 357: ...ced Oscillator 5 V 0 1 F 5 3300 pF OSCIN OSCOUT PLL DACP DACM VPP VDD 1N914 32 RESET VSS 5 5 1 F 20 1 k 100 k 5 V 1N914 Reset Switch To pin 2 of Scan Port Connector To pin 1 of Scan Port Connector opt...

Page 358: ...g to the init code to perform a software reset on parts using resistor trim The resistor trim is set based on the value of fuses blown by the tester when the parts are manufactured The P part does not...

Page 359: ...ING THE RTRIM VALUE THIS PRESERVES THE ZERO VALUE AT PORT 0x2F WHEN READING THE TRIM VALUE should be zero if P part should be non zero if C part WARNING Start off by clearing all the RAM and tags and...

Page 360: ...nd wake up when the clock has reached full speed and is stable if CRO_FLAG mov a0 CROENABLE enable crystal oscillator else Use BIST to determine P or C part BOB 5 00 IN A0 0x2F On uninitialized P part...

Page 361: ...l speed idle go to sleep nop wake up 200 ms later clock running at full speed nop nop Upon reset all ports are set to input and port G output is set low 0x0000 Therefore it remains only to enable the...

Page 362: ...J RPJ Note that this is an example for TI TALKS code version 604 The file extension for the project file is RPJ Click on Project Build to assemble and link the constituent files of the project Then cl...

Page 363: ...AIN_RAM IRX contains definitions for customer RAM Variable and RAM for other modules in the form of RAM IRX files see below should be added here RAM IRX contains definitions for the RAM used by the co...

Page 364: ..._dac_r0 equ dac_buffer 2 1 RESW 1 save_dac_regs equ save_dac_r0 2 1 RESW 5 save_dac_stat equ save_dac_regs 2 5 RESW 1 The above method should be used to declare all customer variables This is illustra...

Page 365: ..._tim2_stat 2 1 save_tim2_a0a equ save_tim2_a0 2 1 Time 2 interrupt variables save_tim2_stat equ save_tim1_a0a 2 1 save_tim2_a0 equ save_tim2_stat 2 1 save_tim2_a0a equ save_tim2_a0 2 1 End of RAM RAME...

Page 366: ...6 12...

Page 367: ...cycle and ordering forms are included in this chapter Topic Page 7 1 Mechanical Information 7 2 7 2 Customer Information Fields in the ROM 7 11 7 3 Speech Development Cycle 7 12 7 4 Device Production...

Page 368: ...connected to test points so the development tool can be connected Since the development tool requires VDD and VSS test points connected to these signals are also needed The application circuits appea...

Page 369: ...3 Comparator for details Scan Port Control Signals SCANIN 42 54 I Scan port data input SCANOUT 38 50 O Scan port data output SCANCLK 41 53 I Scan port clock SYNC 40 52 I Scan port synchronization TEST...

Page 370: ...output SCANCLK 36 38 I Scan port clock SYNC 35 37 I Scan port synchronization TEST 34 36 I C605 test modes The scan port pins must be bonded out on any MSP50C605 production board Consult the Important...

Page 371: ...port data output SCANCLK 36 38 I Scan port clock SYNC 35 37 I Scan port synchronization TEST 34 36 I C605 test modes The scan port pins must be bonded out on any MSP50C601 production board Consult the...

Page 372: ...output SCANCLK 36 38 I Scan port clock SYNC 35 37 I Scan port synchronization TEST 34 36 I C605 test modes The scan port pins must be bonded out on any MSP50C604 production board Consult the Important...

Page 373: ...14 20 17 45 13 80 16 95 50 51 31 30 12 35 TYP 1 03 0 73 0 25 Seating Plane 0 25 MIN Gage Plane 0 38 0 22 80 1 81 100 22 95 23 45 20 20 19 80 2 50 2 90 3 40 MAX 18 85 TYP 0 7 M 0 13 0 65 0 10 NOTES A A...

Page 374: ...0 05 MIN Gage Plane 0 27 33 16 48 1 0 17 49 64 SQ SQ 10 20 11 80 12 20 9 80 7 50 TYP 1 60 MAX 1 45 1 35 0 08 0 50 M 0 08 0 7 NOTES A All linear dimensions are in millimeters B This drawing is subject...

Page 375: ...is shown in Figure 7 3 Figure 7 3 120 Pin Grid Array Package for the Development Device MSP50P614 extra pin 1 2 3 4 5 6 7 8 9 N M L K J H G F E D C B A 10 9 8 7 6 5 4 3 2 1 N M L K J H G F E D C B A...

Page 376: ...tom view RESET scanin PE7 F PC2 PC3 PC4 PE4 PE5 PE6 E PC5 PC6 nc PE0 PE2 PE3 D PC7 nc nc extra nc VSS PE1 C nc nc nc nc PB1 PB5 VSS PA3 PA7 nc nc nc nc B nc nc nc PB0 PB3 PB6 PA0 PA2 PA5 PLL OSCOUT nc...

Page 377: ...000C Assuming these addresses are not specifically read protected by the ROM security they are read accessible to the programmer The fields appear as follows MSP50C614 EPROM Test Area Customer Informa...

Page 378: ...h development cycle Figure 7 5 Speech Development Cycle Speech Specification Speaker Selection Recording Script Preparation Software Design Hardware Design Software Writing Prototype Construction Soft...

Page 379: ...ed by the customer A minimum purchase is required during the first year of production Customer Sends Code in QBN or TITAG format and completes Section 1 of the NPRF TI completes Section 2A of NPRF and...

Page 380: ...QFP MSP50C604 Y Die 7 6 New Product Release Forms NPRF The new product release form is used to track and document all the steps involved in implementing a new speech code onto one of the parent speec...

Page 381: ...TI PRODUCTION PART NUMBER This section is to be completed by TI TI Part Number ___________ CSM614xxxY or CSM614xxxPJM SECTION 2B PACKAGE UNIT SYMBOLIZATION This section is to be completed by the cust...

Page 382: ...____________________ FAX this form to 214 480 7301 Attn Code Release Team SECTION 4 APPROVAL OF PROTOTYPES AND AUTHORIZATION TO START PRODUCTION This section is to be completed by the customer after p...

Page 383: ...__ of format vv rr vv version rr revision numeric values only SECTION 2A ASSIGNMENT OF TI PRODUCTION PART NUMBER This section is to be completed by TI TI Part Number ___________ CSM604xxxY or CSM604xx...

Page 384: ...________ Date _____________________ FAX this form to 214 480 7301 Attn Code Release Team SECTION 4 APPROVAL OF PROTOTYPES AND AUTHORIZATION TO START PRODUCTION This section is to be completed by the c...

Page 385: ...TI PRODUCTION PART NUMBER This section is to be completed by TI TI Part Number ___________ CSM605xxxY or CSM605xxxPJM SECTION 2B PACKAGE UNIT SYMBOLIZATION This section is to be completed by the cust...

Page 386: ...____________________ FAX this form to 214 480 7301 Attn Code Release Team SECTION 4 APPROVAL OF PROTOTYPES AND AUTHORIZATION TO START PRODUCTION This section is to be completed by the customer after p...

Page 387: ...TI PRODUCTION PART NUMBER This section is to be completed by TI TI Part Number ___________ CSM601xxxY or CSM601xxxPJM SECTION 2B PACKAGE UNIT SYMBOLIZATION This section is to be completed by the cust...

Page 388: ...____________________ FAX this form to 214 480 7301 Attn Code Release Team SECTION 4 APPROVAL OF PROTOTYPES AND AUTHORIZATION TO START PRODUCTION This section is to be completed by the customer after p...

Page 389: ...A 1 Appendix A Additional Information This appendix contains additional information for the MSP50C6xx mixed sig nal processor Topic Page A 1 Additional Information A 2 Appendix A...

Page 390: ...Additional Information A 2 A 1 Additional Information For current information regarding the MSP50C6xx devices data sheets de velopment tools etc visit the TI Speech Web site http www ti com sc speech...

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