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Individual Instruction Descriptions
4-163
Assembly Language Instructions
4.14.68
SHLAPL
Shift Left with Accumulate
Syntax
[label]
name
dest, src
[,
mod]
Clock,
clk
Word,
w
With RPT,
clk
Class
SHLAPL
A
n, {adrs}
Table 4–46
Table 4–46
1b
SHLAPL
A
n[~], An[~] [, next A]
1
1
n
R
+3
3
Execution
[premodify AP if
mod specified]
PH, PL
⇐
src << SV
dest
⇐
dest + PL
PC
⇐
PC + 1
Flags Affected
OF, SF, ZF, CF are set accordingly
src is {adrs}:
TAG bit is set accordingly
Opcode
Instructions
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SHLAPL A
n, {adrs}
0
1
1
1
1
0
0
A
n
adrs
x
dma16 (for direct) or offset16 (long relative) [see section 4.13]
SHLAPL A
n[~], An[~] [, next A]
1
1
1
0
0
next A
A
n
1
1
1
0
1
0
A~
~A
Description
Premodify the accumulator pointer if specified. Shift accumulator word or data memory
word pointed by {
adrs} to left n
SV
bits (as specified by the SV register) into a 32-bit
result. This result is zero-filled on the right and either zero-filled or sign-extended on
the left (based on the setting of the extended sign mode (XM) bit in the status register).
The upper 16 bits are latched into the product high (PH) register. The lower 16 bits of
the result [product low (PL) register] is added to the destination accumulator (or its
offset). This instruction propagates the shifted bits to the next accumulator.
Syntax
Description
SHLAPL A
n, {adrs}
Shift data memory word left, add PL to A
n
SHLAPL A
n[~], An[~] [, next A]
Shift A
n[~] left, add PL to An[~]
See Also
SHLAPLS, SHLTPL , SHLTPLS, SHLSPL, SHLSPLS
Example 4.14.68.1
SHLAPL A0, *R4++R5
Shift the word pointed by the byte address stored in R4 by n
SV
bits to the left, add the shifted value (PL)
with accumulator A0, store the result in accumulator A0. Add R5 to R4 and store result in R4. PH holds
the upper 16 bits of the shift.
Example 4.14.68.2
SHLAPL A2, *R1++
Shift the word pointed by the byte address stored in R1 by n
SV
bits to the left, add the shifted value (PL)
with the accumulator (A2), and store the result in accumulator A2. Increment R1 (by 2) . PH holds the
upper 16 bits of the shift.
Example 4.14.68.3
SHLAPL A1, A1, ++A
Preincrement accumulator pointer AP1. Shift the accumulator A1 by n
SV
bits to the left, add the shifted
value (PL) to the accumulator and store the result in accumulator (A1). After execution PH contains the
upper 16 bits of the 32 bit shift.
Summary of Contents for MSP50C614
Page 1: ...MSP50C614 Mixed Signal Processor User s Guide SPSU014 January 2000 Printed on Recycled Paper ...
Page 6: ...vi ...
Page 92: ...3 22 ...
Page 300: ...Instruction Set Summay 4 208 Assembly Language Instructions ...
Page 314: ...Software Emulator 5 14 Figure 5 13 Project Menu Figure 5 14 Project Open Dialog ...
Page 325: ...Software Emulator 5 25 Code Development Tools Figure 5 25 EPROM Programming Dialog ...
Page 331: ...Software Emulator 5 31 Code Development Tools Figure 5 31 Context Sensitive Help System ...
Page 368: ...5 68 ...
Page 394: ...7 12 ...
Page 402: ...A 8 ...
Page 412: ...Packaging B 10 ...