Introduction
B-2
B.1 Introduction
MSP50C604 is a spin off of the core processor MSP50C614. It is targeted as
a slave device. An external microprocessor is needed to interface with
MSP50C604 in slave mode. It can also be used a stand alone device if desired.
B.2 Features
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30k word ROM customer program memory
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8 MHz uDSP core
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2 IO pins can be used as a comparator
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4 pins for synthesizer syncronization
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Host read or write interrupts core
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PLL clock synthesizer
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Resistor trimmed oscillator or 32 kHz crystal
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640 word RAM
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PDM DAC w/direct speaker drive (32 ohm)
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1 bit comparator with edge-detection interrupt service
(IMPORTANT: Not currently supported)
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Serial scan port for in-circuit emulation/monitor/test
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Host Mode
J
14 general-purpose I/O pins
J
Can generate interrupts
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Slave Mode
J
Works as microprocessor peripheral
J
STROBE, R/W lines for host read/write control
J
INPUTREADY, OUTPUTREADY for handshake
B.3 Architecture
The MSP50C604 will use the 6xx device family core, including breakpoint ca-
pability. It has identical instruction sets and uses the same development tool.
MSP50P614 (EPROM device) is used for code development and testing. The
architecture block diagram is shown in Figure B–1.
Summary of Contents for MSP50C614
Page 1: ...MSP50C614 Mixed Signal Processor User s Guide SPSU014 January 2000 Printed on Recycled Paper ...
Page 6: ...vi ...
Page 92: ...3 22 ...
Page 300: ...Instruction Set Summay 4 208 Assembly Language Instructions ...
Page 314: ...Software Emulator 5 14 Figure 5 13 Project Menu Figure 5 14 Project Open Dialog ...
Page 325: ...Software Emulator 5 25 Code Development Tools Figure 5 25 EPROM Programming Dialog ...
Page 331: ...Software Emulator 5 31 Code Development Tools Figure 5 31 Context Sensitive Help System ...
Page 368: ...5 68 ...
Page 394: ...7 12 ...
Page 402: ...A 8 ...
Page 412: ...Packaging B 10 ...