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Individual Instruction Descriptions
4-81
Assembly Language Instructions
See Also
ANDS, ANDB, OR, ORB, ORS, XOR, XORB, XORS
Example 4.14.4.1
AND A3, *R4— –
And word at address in R4 to A3, store result in A3. Decrement value in R4 by 2 (word mode) after the
AND operation.
Example 4.14.4.2
AND A0~, A0, 0xff0f, – –A
Predecrement accumulator pointer AP0. And immediate value 0xff0f to register accumulator A0, store
result in accumulator A0~.
Example 4.14.4.3
AND TF2, *0x0020
AND global flag bit at RAM word location 0x0020 to TF2 in the STAT. Store result in the TF2 bit in the
STAT register. Note that {flagadrs} cannot exceed values greater than *0x003F.
Example 4.14.4.4
AND TF1, TF2
AND TF1 with TF2 bit in the STAT register and store result in TF1.
Summary of Contents for MSP50C614
Page 1: ...MSP50C614 Mixed Signal Processor User s Guide SPSU014 January 2000 Printed on Recycled Paper ...
Page 6: ...vi ...
Page 92: ...3 22 ...
Page 300: ...Instruction Set Summay 4 208 Assembly Language Instructions ...
Page 314: ...Software Emulator 5 14 Figure 5 13 Project Menu Figure 5 14 Project Open Dialog ...
Page 325: ...Software Emulator 5 25 Code Development Tools Figure 5 25 EPROM Programming Dialog ...
Page 331: ...Software Emulator 5 31 Code Development Tools Figure 5 31 Context Sensitive Help System ...
Page 368: ...5 68 ...
Page 394: ...7 12 ...
Page 402: ...A 8 ...
Page 412: ...Packaging B 10 ...