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Reduced Power Modes
2-37
MSP50C614 Architecture
Table 2–3. Programmable Bits Needed to Control Reduced Power Modes
→
deeper sleep
…
relatively less power
→
Control Bit
Label for
Control Bit
LIGHT
MID
DEEP
Idle state clock control
bit 10
ClkSpdCtrl register (0x3D)
A
0
1
1
Enable reference oscillator
bit 09 : CRO or
bit 08 : RTO
ClkSpdCtrl register (0x3D)
B
1
1
0
ARM
bit 14
IntGenCtrl register (0x38)
C
0
1
1
Enable PDM pulsing
bit 02
DAC Control register (0x34)
D
Should be cleared before any IDLE instruction.
IDLE instruction
(executes the mode)
E
Same instruction is used to engage any of the modes.
PLL multiplier
bits 07 through 00
ClkSpdCtrl register (0x3D)
F
Programmed value is 0
…
255 .
Summary of Contents for MSP50C614
Page 1: ...MSP50C614 Mixed Signal Processor User s Guide SPSU014 January 2000 Printed on Recycled Paper ...
Page 6: ...vi ...
Page 92: ...3 22 ...
Page 300: ...Instruction Set Summay 4 208 Assembly Language Instructions ...
Page 314: ...Software Emulator 5 14 Figure 5 13 Project Menu Figure 5 14 Project Open Dialog ...
Page 325: ...Software Emulator 5 25 Code Development Tools Figure 5 25 EPROM Programming Dialog ...
Page 331: ...Software Emulator 5 31 Code Development Tools Figure 5 31 Context Sensitive Help System ...
Page 368: ...5 68 ...
Page 394: ...7 12 ...
Page 402: ...A 8 ...
Page 412: ...Packaging B 10 ...