Texas Instruments MSP432P401R Manual Download Page 163

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Py.x/USCI/Mod/Cp.q

PySEL1.x

PyDIR.x

PyIN.x

To modules

From USCI

PyOUT.x

DVSS

DVCC

To Comparator

From Comparator

Pad Logic

Bus

Keeper

Direction
0: Input
1: Output

CPD.q

PyREN.x

0 1

0 0

1 0

1 1

PySEL0.x

0 1

0 0

1 0

1 1

From module

DVSS

From USCI

163

MSP432P401R, MSP432P401M

www.ti.com

SLAS826F – MARCH 2015 – REVISED MARCH 2017

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MSP432P401R MSP432P401M

Detailed Description

6.12.17 Port P8 (P8.0 and P8.1) Input/Output With Schmitt Trigger

Figure 6-13

shows the port diagram.

Table 6-78

summarizes the selection of the pin functions.

Functional representation only.

Figure 6-13. Py.x/USCI/Mod/Cp.q Pin Diagram

Summary of Contents for MSP432P401R

Page 1: ...5 25 nA Development Kits and Software See Tools and Software MSP EXP432P401R LaunchPad Development Kit MSP TS432PZ100 100 Pin Target Board SimpleLink MSP432 Software Development Kit SDK Operating Characteristics Wide Supply Voltage Range 1 62 V to 3 7 V Temperature Range Ambient 40 C to 85 C Flexible Clocking Features Tunable Internal DCO up to 48 MHz 32 768 kHz Low Frequency Crystal Support LFXT ...

Page 2: ... developers to add high precision analog and memory extension to applications based on SimpleLink wireless connectivity solutions The MSP432P401x devices are part of the SimpleLink microcontroller MCU platform which consists of Wi Fi Bluetooth low energy Sub 1 GHz and host MCUs All share a common easy to use development environment with a single core software development kit SDK and rich tool set ...

Page 3: ...M 6KB CPU MPU NVIC SysTick FPB DWT ARM Cortex M4F ITM TPIU JTAG SWD SRAM includes Backup Memory 64KB 32KB ROM Peripheral Driver Library 32KB Copyright 2016 Texas Instruments Incorporated 3 MSP432P401R MSP432P401M www ti com SLAS826F MARCH 2015 REVISED MARCH 2017 Submit Documentation Feedback Product Folder Links MSP432P401R MSP432P401M Device Overview Copyright 2015 2017 Texas Instruments Incorpor...

Page 4: ...5 Typical Characteristics of Active Mode Currents for Fibonacci Program 35 5 16 Typical Characteristics of Active Mode Currents for While 1 Program 36 5 17 Typical Characteristics of Low Frequency Active Mode Currents for CoreMark Program 37 5 18 Current Consumption in LDO Based LPM0 Modes 38 5 19 Current Consumption in DC DC Based LPM0 Modes 38 5 20 Current Consumption in Low Frequency LPM0 Modes...

Page 5: ...sion History NOTE Page numbers for previous revisions may differ from page numbers in the current version Changes from July 26 2016 to March 7 2017 Page Added SimpleLink branding including updates to the titles of referenced documents 1 Reorganized contents of Section 1 1 Features 1 Updated Section 1 2 Applications 2 Updated Section 1 3 Description 2 Updated lists of software and tools in Section ...

Page 6: ...tput generators available For example a number sequence of 3 5 would represent two instantiations of Timer_A the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators respectively Table 3 1 Device Comparison 1 DEVICE FLASH KB SRAM KB ADC14 Channels COMP_E0 Channels COMP_E1 Channels Timer_A 2 eUSCI 20 mA DRIVE I O TOTAL I Os PACKAGE C...

Page 7: ... core are optimized for Internet of Things sensor node applications With an integrated 14 bit ADC the family enables acquisition and processing of high precision signals without sacrificing power and is an optimal host MCU for TI s SimpleLink wireless connectivity solutions Companion Products for MSP432P401R Review products that are frequently purchased or used with this product Reference Designs ...

Page 8: ...4 A1 69 P5 5 A0 70 P5 6 TA2 1 VREF VeREF C1 7 71 P5 7 TA2 2 VREF VeREF C1 6 72 DVSS2 73 DVCC2 74 P9 2 TA3 3 75 P9 3 TA3 4 76 P6 2 UCB1STE C1 5 77 P6 3 UCB1CLK C1 4 78 P6 4 UCB1SIMO UCB1SDA C1 3 79 P6 5 UCB1SOMI UCB1SCL C1 2 80 P6 6 TA2 3 UCB3SIMO UCB3SDA C1 1 81 P6 7 TA2 4 UCB3SOMI UCB3SCL C1 0 82 DVSS3 83 RSTn NMI 84 AVSS2 85 PJ 2 HFXOUT 86 PJ 3 HFXIN 87 AVCC2 88 P7 0 PM_SMCLK PM_DMAE0 89 P7 1 PM...

Page 9: ...4 1 P4 0 P7 4 P7 6 P3 0 P3 3 P3 6 PJ 0 PJ 1 DCOR P6 0 PJ 2 P6 3 DVCC2 AVCC2 P1 3 AVSS2 P2 2 P2 0 AVSS3 DVSS2 P2 4 P2 3 AVSS1 AVCC1 P4 5 P7 7 P4 6 9 MSP432P401R MSP432P401M www ti com SLAS826F MARCH 2015 REVISED MARCH 2017 Submit Documentation Feedback Product Folder Links MSP432P401R MSP432P401M Terminal Configuration and Functions Copyright 2015 2017 Texas Instruments Incorporated Figure 4 2 show...

Page 10: ...2 3 UCB3SIMO UCB3SDA C1 1 50 P6 7 TA2 4 UCB3SOMI UCB3SCL C1 0 51 DVSS3 52 RSTn NMI 53 AVSS2 54 PJ 2 HFXOUT 55 PJ 3 HFXIN 56 AVCC2 57 P7 0 PM_SMCLK PM_DMAE0 58 P7 1 PM_C0OUT PM_TA0CLK 59 P7 2 PM_C1OUT PM_TA1CLK 60 P7 3 PM_TA0 0 61 PJ 4 TDI 62 PJ 5 TDO SWO 63 SWDIOTMS 64 SWCLKTCK 10 MSP432P401R MSP432P401M SLAS826F MARCH 2015 REVISED MARCH 2017 www ti com Submit Documentation Feedback Product Folder...

Page 11: ...AL NAME 2 3 SIGNAL TYPE 4 BUFFER TYPE 5 POWER SOURCE 6 RESET STATE AFTER POR 7 PZ ZXH RGC 1 N A N A P10 1 RD I O LVCMOS DVCC OFF UCB3CLK I O LVCMOS DVCC N A 2 N A N A P10 2 RD I O LVCMOS DVCC OFF UCB3SIMO I O LVCMOS DVCC N A UCB3SDA I O LVCMOS DVCC N A 3 N A N A P10 3 RD I O LVCMOS DVCC OFF UCB3SOMI I O LVCMOS DVCC N A UCB3SCL I O LVCMOS DVCC N A 4 A1 1 P1 0 RD I O LVCMOS DVCC OFF UCA0STE I O LVCM...

Page 12: ...DVCC OFF PM_TA0 3 I O LVCMOS DVCC N A 23 H1 N A P2 7 RD I O LVCMOS DVCC OFF PM_TA0 4 I O LVCMOS DVCC N A 24 N A N A P10 4 RD I O LVCMOS DVCC OFF TA3 0 I O LVCMOS DVCC N A C0 7 I Analog DVCC N A 25 N A N A P10 5 RD I O LVCMOS DVCC OFF TA3 1 I O LVCMOS DVCC N A C0 6 I Analog DVCC N A 26 J1 N A P7 4 RD I O LVCMOS DVCC OFF PM_TA1 4 I O LVCMOS DVCC N A C0 5 I Analog DVCC N A 27 H2 N A P7 5 RD I O LVCMO...

Page 13: ...VCC N A 39 H6 26 P3 7 RD I O LVCMOS DVCC OFF PM_UCB2SOMI I O LVCMOS DVCC N A PM_UCB2SCL I LVCMOS DVCC N A 40 E5 27 AVSS3 Power N A N A 41 J6 28 PJ 0 RD I O LVCMOS DVCC OFF LFXIN I Analog DVCC N A 42 J7 29 PJ 1 RD I O LVCMOS DVCC OFF LFXOUT O Analog DVCC N A 43 F5 30 AVSS1 Power N A N A 44 J8 31 DCOR Analog N A N A 45 F6 32 AVCC1 Power N A N A 46 N A N A P8 2 RD I O LVCMOS DVCC OFF TA3 2 I O LVCMOS...

Page 14: ... LVCMOS DVCC OFF HSMCLK O LVCMOS DVCC N A SVMHOUT O LVCMOS DVCC N A A9 I Analog DVCC N A 61 F7 36 P4 5 RD I O LVCMOS DVCC OFF A8 I Analog DVCC N A 62 F8 37 P4 6 RD I O LVCMOS DVCC OFF A7 I Analog DVCC N A 63 F9 38 P4 7 RD I O LVCMOS DVCC OFF A6 I Analog DVCC N A 64 E7 39 P5 0 RD I O LVCMOS DVCC OFF A5 I Analog DVCC N A 65 E8 40 P5 1 RD I O LVCMOS DVCC OFF A4 I Analog DVCC N A 66 E9 41 P5 2 RD I O ...

Page 15: ...VCC N A C1 3 I Analog DVCC N A 79 A7 N A P6 5 RD I O LVCMOS DVCC OFF UCB1SOMI I O LVCMOS DVCC N A UCB1SCL I O LVCMOS DVCC N A C1 2 I Analog DVCC N A 80 B8 49 P6 6 RD I O LVCMOS DVCC OFF TA2 3 I O LVCMOS DVCC N A UCB3SIMO I O LVCMOS DVCC N A UCB3SDA I O LVCMOS DVCC N A C1 1 I Analog DVCC N A 81 B7 50 P6 7 RD I O LVCMOS DVCC OFF TA2 4 I O LVCMOS DVCC N A UCB3SOMI I O LVCMOS DVCC N A UCB3SCL I O LVCM...

Page 16: ... DVCC N A 92 B3 61 PJ 4 I O LVCMOS DVCC N A TDI RD I LVCMOS DVCC PU 93 A3 62 PJ 5 I O LVCMOS DVCC N A TDO RD O LVCMOS DVCC N A SWO O LVCMOS DVCC N A 94 B2 63 SWDIOTMS I O LVCMOS DVCC PU 95 A2 64 SWCLKTCK I LVCMOS DVCC PD 96 N A N A P9 4 RD I O LVCMOS DVCC OFF UCA3STE I O LVCMOS DVCC N A 97 N A N A P9 5 RD I O LVCMOS DVCC OFF UCA3CLK I O LVCMOS DVCC N A 98 N A N A P9 6 RD I O LVCMOS DVCC OFF UCA3RX...

Page 17: ...nput A8 A9 60 G9 35 I ADC analog input A9 A10 59 G8 34 I ADC analog input A10 A11 58 G7 33 I ADC analog input A11 A12 57 H8 N A I ADC analog input A12 A13 56 H9 N A I ADC analog input A13 A14 55 H7 N A I ADC analog input A14 A15 54 J9 N A I ADC analog input A15 A16 53 N A N A I ADC analog input A16 A17 52 N A N A I ADC analog input A17 A18 51 N A N A I ADC analog input A18 A19 50 N A N A I ADC ana...

Page 18: ...5 C1 6 71 C9 46 I Comparator_E1 input 6 C1 7 70 D9 45 I Comparator_E1 input 7 Debug SWCLKTCK 95 A2 64 I Serial wire clock input SWCLK JTAG clock input TCK SWDIOTMS 94 B2 63 I O Serial wire data input output SWDIO JTAG test mode select TMS SWO 93 A3 62 O Serial wire trace output TDI 92 B3 61 I JTAG test data input TDO 93 A3 62 O JTAG test data output GPIO P1 0 4 A1 1 I O General purpose digital I O...

Page 19: ...1 G1 N A I O General purpose digital I O with port interrupt and wake up capability and with reconfigurable port mapping secondary function P2 6 22 G2 N A I O General purpose digital I O with port interrupt and wake up capability and with reconfigurable port mapping secondary function P2 7 23 H1 N A I O General purpose digital I O with port interrupt and wake up capability and with reconfigurable ...

Page 20: ... 1 65 E8 40 I O General purpose digital I O with port interrupt and wake up capability P5 2 66 E9 41 I O General purpose digital I O with port interrupt and wake up capability P5 3 67 D7 42 I O General purpose digital I O with port interrupt and wake up capability P5 4 68 D8 43 I O General purpose digital I O with port interrupt and wake up capability P5 5 69 C8 44 I O General purpose digital I O ...

Page 21: ...g secondary function RD P8 0 30 H3 17 I O General purpose digital I O P8 1 31 G4 18 I O General purpose digital I O P8 2 46 N A N A I O General purpose digital I O P8 3 47 N A N A I O General purpose digital I O P8 4 48 N A N A I O General purpose digital I O P8 5 49 N A N A I O General purpose digital I O P8 6 50 N A N A I O General purpose digital I O P8 7 51 N A N A I O General purpose digital ...

Page 22: ... FUNCTION SIGNAL NAME SIGNAL NO 1 SIGNAL TYPE 2 DESCRIPTION PZ ZXH RGC I2 C UCB0SCL 11 E1 8 I O I2 C clock eUSCI_B0 I2 C mode UCB0SDA 10 D1 7 I O I2 C data eUSCI_B0 I2 C mode UCB1SCL 79 A7 N A I O I2 C clock eUSCI_B1 I2 C mode UCB1SDA 78 A8 N A I O I2 C data eUSCI_B1 I2 C mode UCB3SCL 3 N A N A I O I2 C clock eUSCI_B3 I2 C mode UCB3SCL 81 B7 50 I O I2 C clock eUSCI_B3 I2 C mode UCB3SDA 2 N A N A I...

Page 23: ...lt mapping TA1 CCR2 capture CCI2A input compare Out2 PM_TA1 3 27 H2 N A I O Default mapping TA1 CCR3 capture CCI3A input compare Out3 PM_TA1 4 26 J1 N A I O Default mapping TA1 CCR4 capture CCI4A input compare Out4 PM_TA1CLK 90 B4 59 I Default mapping TA1 input clock PM_UCA1CLK 17 F1 14 I O Default mapping Clock signal input eUSCI_A1 SPI slave mode Clock signal output eUSCI_A1 SPI master mode PM_U...

Page 24: ...mode PM_UCB2SOMI 39 H6 26 I O Default mapping Slave out master in eUSCI_B2 SPI mode PM_UCB2STE 36 H5 23 I O Default mapping Slave transmit enable eUSCI_B2 SPI mode Power AVCC1 45 F6 32 Analog power supply AVCC2 87 D5 56 Analog power supply AVSS1 43 F5 30 Analog ground supply AVSS2 84 D6 53 Analog ground supply AVSS3 40 E5 27 Analog ground supply DVCC1 13 D2 10 Digital power supply DVCC2 73 C6 48 D...

Page 25: ... I O Slave in master out eUSCI_B0 SPI mode UCB0SOMI 11 E1 8 I O Slave out master in eUSCI_B0 SPI mode UCB0STE 8 D3 5 I O Slave transmit enable eUSCI_B0 SPI mode UCB1CLK 77 B9 N A I O Clock signal input eUSCI_B1 SPI slave mode Clock signal output eUSCI_B1 SPI master mode UCB1SIMO 78 A8 N A I O Slave in master out eUSCI_B1 SPI mode UCB1SOMI 79 A7 N A I O Slave out master in eUSCI_B1 SPI mode UCB1STE...

Page 26: ...1A input compare Out1 TA2 2 71 C9 46 I O TA2 CCR2 capture CCI2A input compare Out2 TA2 3 80 B8 49 I O TA2 CCR3 capture CCI3A input compare Out3 TA2 4 81 B7 50 I O TA2 CCR4 capture CCI4A input compare Out4 TA2CLK 58 G7 33 I TA2 input clock TA3 0 24 N A N A I O TA3 CCR0 capture CCI0A input compare Out0 TA3 1 25 N A N A I O TA3 CCR1 capture CCI1A input compare Out1 TA3 2 46 N A N A I O TA3 CCR2 captu...

Page 27: ... Purpose I Os See Typical Characteristics Power DVCC 3 3 0 V N N A N A N A SVSMH enables hysteresis on DVCC Power AVCC 3 3 0 V N N A N A N A Power DVSS and AVSS 3 0 V N N A N A N A 1 For any unused pin with a secondary function that is shared with general purpose I O follow the guidelines for the Px 0 to Px 7 pins 4 6 Connection for Unused Pins Table 4 4 lists the correct termination of all unused...

Page 28: ...ept DVSS3 pass HBM up to 1000 V The DVSS3 pin is used for TI internal test purposes Connect the DVSS3 pin to supply ground on the customer application board 3 JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process Pins listed as 250 V may actually have higher performance 5 2 ESD Ratings VALUE UNIT V ESD Electrostatic discharge Human body model HBM...

Page 29: ...llowed DCR for LVSW 150 350 mΩ ISAT LVSW LVSW saturation current 700 mA 1 Flash remains active only in active modes and LPM0 modes 2 Low frequency active low frequency LPM0 LPM3 LPM4 and LPM3 5 modes are based on LDO only 3 When VCC falls below the specified MIN value the DC DC operation switches to LDO automatically as long as the VCC drop is slower than the rate that is reliably detected See Tab...

Page 30: ...F_VCORE0 Low frequency mode with LDO as the active regulator 0 128 kHz fAM_LF_VCORE1 AM_LF_VCORE1 Low frequency mode with LDO as the active regulator 0 128 kHz 1 Only RTC and WDT can be active 5 7 Operating Mode Peripheral Frequency Ranges over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER OPERATING MODE DESCRIPTION MIN MAX UNIT fAM_LPM0_V...

Page 31: ... Outputs do not source or sync any current 5 9 Current Consumption During Device Reset over recommended ranges of supply voltage and operating free air temperature unless otherwise noted 1 2 3 PARAMETER VCC MIN TYP MAX UNIT IRESET Current during device reset 2 2 V 510 µA 3 0 V 600 850 1 MCLK sourced by DCO 2 Current measured into VCC 3 All other input pins tied to 0 V or VCC Outputs do not source ...

Page 32: ...V 430 550 1100 1280 1880 2140 2650 3000 3290 3700 4020 4500 4720 5300 µA IAM_DCDC_VCORE0 SRAM 9 SRAM 3 0 V 370 450 680 780 1040 1180 1410 1600 µA IAM_DCDC_VCORE1 SRAM 9 SRAM 3 0 V 390 510 790 940 1250 1440 1720 1960 2200 2480 2670 3000 3050 3420 µA 1 Current measured into VCC 2 All other input pins tied to 0 V or VCC Outputs do not source or sync any current 3 MCLK HSMCLK and SMCLK sourced by REFO...

Page 33: ...1 33 MSP432P401R MSP432P401M www ti com SLAS826F MARCH 2015 REVISED MARCH 2017 Submit Documentation Feedback Product Folder Links MSP432P401R MSP432P401M Specifications Copyright 2015 2017 Texas Instruments Incorporated 5 13 Typical Characteristics of Active Mode Currents for CoreMark Program Flash Execution VCC 3 V TA 25 C Figure 5 1 Frequency vs Current Consumption SRAM Execution VCC 3 V TA 25 C...

Page 34: ...34 MSP432P401R MSP432P401M SLAS826F MARCH 2015 REVISED MARCH 2017 www ti com Submit Documentation Feedback Product Folder Links MSP432P401R MSP432P401M Specifications Copyright 2015 2017 Texas Instruments Incorporated 5 14 Typical Characteristics of Active Mode Currents for Prime Number Program Flash Execution VCC 3 V TA 25 C Figure 5 5 Frequency vs Current Consumption SRAM Execution VCC 3 V TA 25...

Page 35: ...35 MSP432P401R MSP432P401M www ti com SLAS826F MARCH 2015 REVISED MARCH 2017 Submit Documentation Feedback Product Folder Links MSP432P401R MSP432P401M Specifications Copyright 2015 2017 Texas Instruments Incorporated 5 15 Typical Characteristics of Active Mode Currents for Fibonacci Program Flash Execution VCC 3 V TA 25 C Figure 5 9 Frequency vs Current Consumption SRAM Execution VCC 3 V TA 25 C ...

Page 36: ... 36 MSP432P401R MSP432P401M SLAS826F MARCH 2015 REVISED MARCH 2017 www ti com Submit Documentation Feedback Product Folder Links MSP432P401R MSP432P401M Specifications Copyright 2015 2017 Texas Instruments Incorporated 5 16 Typical Characteristics of Active Mode Currents for While 1 Program Flash Execution VCC 3 V TA 25 C Figure 5 13 Frequency vs Current Consumption SRAM Execution VCC 3 V TA 25 C ...

Page 37: ... www ti com SLAS826F MARCH 2015 REVISED MARCH 2017 Submit Documentation Feedback Product Folder Links MSP432P401R MSP432P401M Specifications Copyright 2015 2017 Texas Instruments Incorporated 5 17 Typical Characteristics of Low Frequency Active Mode Currents for CoreMark Program Flash Execution TA 25 C MCLK 128 kHz Figure 5 17 Supply Voltage vs Current Consumption SRAM Execution TA 25 C MCLK 128 k...

Page 38: ...nc any current 4 CPU is off Flash and SRAM not accessed 5 All SRAM banks are active 6 All peripherals are inactive 5 19 Current Consumption in DC DC Based LPM0 Modes over recommended operating free air temperature unless otherwise noted 1 2 3 4 5 6 PARAMETER VCC MCLK 1 MHz MCLK 8 MHz MCLK 16 MHz MCLK 24 MHz MCLK 32 MHz MCLK 40 MHz MCLK 48 MHz UNIT TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX TY...

Page 39: ... 2 V 0 85 1 07 1 55 2 89 μA 3 0 V 0 95 1 16 1 35 1 64 2 98 5 6 ILPM3_VCORE1_RTCLF 7 8 2 2 V 0 72 0 93 1 47 2 95 μA 3 0 V 0 75 0 95 1 35 1 5 2 98 6 ILPM3_VCORE1_RTCREFO 9 8 2 2 V 1 04 1 3 1 87 3 34 μA 3 0 V 1 14 1 4 1 7 1 96 3 44 6 5 ILPM4_VCORE0 10 2 2 V 0 37 0 48 0 92 2 19 μA 3 0 V 0 4 0 5 0 65 0 94 2 2 4 8 ILPM4_VCORE1 10 2 2 V 0 54 0 7 1 2 2 58 μA 3 0 V 0 56 0 72 0 98 1 23 2 6 5 6 1 Current mea...

Page 40: ... junction to board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature as described in JESD51 8 6 The junction to case bottom thermal resistance is obtained by simulating a cold plate test on the exposed power pad No specific JEDEC standard test exists but a close description can be found in the ANSI SEMI standard G30 88 5 24...

Page 41: ...e 5 2 lists the latencies to recover from an external reset applied on RSTn pin 1 External reset is applied on RSTn pin and the latency is measured from release of external reset to start of user application code Table 5 2 External Reset Recovery Latencies 1 over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS MIN MAX UNIT tA...

Page 42: ...E1 to AM_LDO_VCORE0 MCLK frequency 24 MHz 4 5 µs tAMLDO0_AMDCDC0 AM_LDO_VCORE0 AM_DCDC_VCORE0 Transition from AM_LDO_VCORE0 to AM_DCDC_VCORE0 MCLK frequency 24 MHz 20 30 µs tAMDCDC0_AMLDO0 AM_DCDC_VCORE0 AM_LDO_VCORE0 Transition from AM_DCDC_VCORE0 to AM_LDO_VCORE0 MCLK frequency 24 MHz 10 15 µs tAMLDO1_AMDCDC1 AM_LDO_VCORE1 AM_DCDC_VCORE1 Transition from AM_LDO_VCORE1 to AM_DCDC_VCORE1 MCLK frequ...

Page 43: ...LPM0LDOx 1 AM_LDO_VCOREx LPM0_LDO_VCOREx Transition from AM_LDO_VCORE0 or AM_LDO_VCORE1 to LPM0_LDO_VCORE0 or LPM0_LDO_VCORE1 1 MCLK cycles tLPM0LDOx_AMLDOx 2 LPM0_LDO_VCOREx AM_LDO_VCOREx Transition from LPM0_LDO_VCORE0 or LPM0_LDO_VCORE1 to AM_LDO_VCORE0 or AM_LDO_VCORE1 through I O interrupt 3 4 MCLK cycles tAMDCDCx_LPM0DCDCx 1 AM_DCDC_VCOREx LPM0_DCDC_VCOREx Transition from AM_DCDC_VCORE0 or A...

Page 44: ...glitch filter type I O GLTFLT_EN 1 SELM 3 DCO frequency 24 MHz 9 10 µs tAMLDO1_LPMx1 1 AM_LDO_VCORE1 LPM3_LPM4_VCORE1 Transition from AM_LDO_VCORE1 to LPM3 or LPM4 at VCORE1 SELM 3 DCO frequency 48 MHz 21 23 µs tLPMx1_AMLDO1_NORIO 2 LPM3_LPM4_VCORE1 AM_LDO_VCORE1 Transition from LPM3 or LPM4 at VCORE1 to AM_LDO_VCORE1 through wake up event from nonglitch filter type I O SELM 3 DCO frequency 48 MHz...

Page 45: ..._DCDC_VCORE0 or AM_DCDC_VCORE1 to LPM3 5 35 50 µs tAMLFx_LPM3 5 1 AM_LF_VCOREx LPM3 5 Transition from AM_LF_VCORE0 or AM_LF_VCORE1 to LPM3 5 225 250 µs tAMLDOx_LPM4 5 2 AM_LDO_VCOREx LPM4 5 Transition from AM_LDO_VCORE0 or AM_LDO_VCORE1 to LPM4 5 25 30 µs tAMDCDCx_LPM4 5 2 AM_DCDC_VCOREx LPM4 5 Transition from AM_DCDC_VCORE0 or AM_DCDC_VCORE1 to LPM4 5 35 50 µs tAMLFx_LPM4 5 2 AM_LF_VCOREx LPM4 5 ...

Page 46: ...eeded 5 Oscillation allowance is based on a safety factor of 5 for recommended crystals The oscillation allowance is a function of the LFXTDRIVE settings and the effective load In general comparable oscillator allowance can be achieved based on the following guidelines but should be evaluated based on the actual crystal selected for the application For LFXTDRIVE 0 CL eff 3 7 pF For LFXTDRIVE 1 6 p...

Page 47: ...up counter 9 Frequencies above the MAX specification do not set the fault flag Frequencies in between the MIN and MAX specification may set the flag A static condition or stuck at fault condition will set the fault flag 10 Measured with logic level input frequency but also applies to operation with crystals CLFXIN Integrated load capacitance at LFXIN terminal 6 7 2 pF CLFXOUT Integrated load capac...

Page 48: ... HFFREQ 1 CL eff 16 pF Typical ESR and CSHUNT 100 fOSC 16 MHz HFXTBYPASS 0 HFXTDRIVE 1 HFFREQ 2 CL eff 16 pF Typical ESR and CSHUNT 180 fOSC 24 MHz HFXTBYPASS 0 HFXTDRIVE 1 HFFREQ 3 CL eff 16 pF Typical ESR and CSHUNT 260 fOSC 32 MHz HFXTBYPASS 0 HFXTDRIVE 1 HFFREQ 4 CL eff 16 pF Typical ESR and CSHUNT 320 fOSC 40 MHz HFXTBYPASS 0 HFXTDRIVE 1 HFFREQ 5 CL eff 16 pF Typical ESR and CSHUNT 480 fOSC 4...

Page 49: ...a safety factor of 5 for recommended crystals OAHFXT Oscillation allowance for HFXT crystals 3 HFXTBYPASS 0 HFXTDRIVE 0 HFFREQ 0 fHFXT HF 1 MHz CL eff 16 pF 1225 5000 Ω HFXTBYPASS 0 HFXTDRIVE 1 HFFREQ 0 fHFXT HF 4 MHz CL eff 16 pF 640 1250 HFXTBYPASS 0 HFXTDRIVE 1 HFFREQ 1 fHFXT HF 8 MHz CL eff 16 pF 360 750 HFXTBYPASS 0 HFXTDRIVE 1 HFFREQ 2 fHFXT HF 16 MHz CL eff 16 pF 200 425 HFXTBYPASS 0 HFXTDR...

Page 50: ...hat the recommended effective load capacitance of the selected crystal is met 7 Frequencies above the MAX specification do not set the fault flag Frequencies in between the MIN and MAX might set the flag A static condition or stuck at fault condition will set the flag 8 Measured with logic level input frequency but also applies to operation with crystals tSTART HFXT Start up time 4 fOSC 1 MHz HFXT...

Page 51: ...CTR DCO center frequency accuracy for range 3 with calibrated factory settings Internal resistor mode DCORSEL 3 DCOTUNE 0 11 541 12 12 459 MHz External resistor mode DCORSEL 3 DCOTUNE 0 11 856 12 12 144 fRSEL4_CTR DCO center frequency accuracy for range 4 with calibrated factory settings Internal resistor mode DCORSEL 4 DCOTUNE 0 23 082 24 24 918 MHz External resistor mode DCORSEL 4 DCOTUNE 0 23 7...

Page 52: ...STEP Step size Step size of the DCO 0 2 tDCO_SETTLE_RANGE DCO settling from worst case DCORSELn to DCORSELm DCO settled to within 1 5 of steady state frequency 10 µs tDCO_SETTLE_TUNE DCO settling worst case DCOTUNEn to DCOTUNEm within any DCORSEL setting DCO settled to within 1 5 of steady state frequency 10 µs tSTART DCO start up time 4 DCO settled to within 0 5 of steady state frequency 5 µs Tab...

Page 53: ...V to 3 7 V MIN 1 62 V to 3 7 V MIN 1 62 V to 3 7 V 3 7 V 1 62 V Table 5 14 Internal Reference Low Frequency Oscillator REFO in 32 768 kHz Mode 1 over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT IREFO REFO current consumption 2 0 6 µA fREFO REFO frequency calibrated 32 768 kHz REFO absolute tolerance c...

Page 54: ... IMODOSC Current consumption 1 50 µA fMODOSC MODOSC frequency 23 25 27 MHz dfMODOSC dT MODOSC frequency temperature drift 2 0 02 dfMODOSC dV CC MODOSC frequency supply voltage drift 3 0 3 V DCMODOSC Duty cycle 40 50 60 Table 5 17 lists the characteristics of the system oscillator SYSOSC 1 Current measured on AVCC supply 2 Calculated using the box method MAX 40 C to 85 C MIN 40 C to 85 C MIN 40 C t...

Page 55: ...LPM34 Static VCORE voltage Level 1 in LPM3 and LPM4 modes Device power modes LPM3 LPM4 1 27 1 4 1 53 V VCORE0 LPM35 Static VCORE voltage Level 0 in LPM3 5 mode Device power mode LPM3 5 1 08 1 2 1 32 V IINRUSH ST Inrush current at start up Device power up 200 mA IPEAK LDO Peak current drawn by LDO from DVCC 350 mA ISC coreLDO Short circuit current limit for core LDO Measured when output is shorted ...

Page 56: ...SVSMHLP 1 200 400 nA SVSMH current consumption high performance mode SVSMHOFF 0 SVSMHLP 0 7 10 μA VSVSMH HP SVSMH threshold level during high performance mode falling DVCC SVSMHOFF 0 SVSMHLP 0 SVSMHTH 0 DC dDVCC dt 1V s 1 59 1 64 1 71 V SVSMHOFF 0 SVSMHLP 0 SVSMHTH 1 DC dDVCC dt 1V s 1 59 1 64 1 71 SVSMHOFF 0 SVSMHLP 0 SVSMHTH 2 DC dDVCC dt 1V s 1 59 1 64 1 71 SVSMHOFF 0 SVSMHLP 0 SVSMHTH 3 DC dDV...

Page 57: ...cation Otherwise SVSMH may trip causing the device to reset and wake up from the low power mode VSVSMH LP SVSMH threshold level Low Power Mode falling DVCC SVSMHOFF 0 SVSMHLP 1 SVSMHTH 0 DC dDVCC dt 1V s 1 55 1 62 1 71 V SVSMHOFF 0 SVSMHLP 1 SVSMHTH 1 DC dDVCC dt 1V s 1 55 1 62 1 71 SVSMHOFF 0 SVSMHLP 1 SVSMHTH 2 DC dDVCC dt 1V s 1 55 1 62 1 71 SVSMHOFF 0 SVSMHLP 1 SVSMHTH 3 DC dDVCC dt 1V s 2 0 2...

Page 58: ...h Normal and High Drive I Os over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VIT Positive going input threshold voltage 2 2 V 0 99 1 65 V 3 V 1 35 2 25 VIT Negative going input threshold voltage 2 2 V 0 55 1 21 V 3 V 0 75 1 65 Vhys Input voltage hysteresis VIT VIT 2 2 V 0 32 0 84 V 3 V 0 4 1 0 RPull ...

Page 59: ... VCC Table 5 23 Digital Outputs Normal I Os over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS VCC MIN MAX UNIT VOH High level output voltage I OHmax 1 mA 1 2 2 V VCC 0 25 VCC V I OHmax 3 mA 2 VCC 0 60 VCC I OHmax 2 mA 1 3 0 V VCC 0 25 VCC I OHmax 6 mA 2 VCC 0 60 VCC VOL Low level output voltage I OLmax 1 mA 1 2 2 V VSS VSS...

Page 60: ...ise noted PARAMETER TEST CONDITIONS VCC MIN MAX UNIT VOH High level output voltage I OHmax 5 mA 1 2 2 V VCC 0 25 VCC V I OHmax 15 mA 2 VCC 0 60 VCC I OHmax 10 mA 1 3 0 V VCC 0 25 VCC I OHmax 20 mA 2 VCC 0 50 VCC VOL Low level output voltage I OLmax 5 mA 1 2 2 V VSS VSS 0 25 V I OLmax 15 mA 2 VSS VSS 0 60 I OLmax 10 mA 1 3 0 V VSS VSS 0 25 I OLmax 20 mA 2 VSS VSS 0 50 fPx y Port output frequency wi...

Page 61: ...0 9 1 2 1 5 1 8 2 1 2 4 2 7 3 3 0 3 6 9 12 15 18 21 24 27 30 D010 TA 25 C TA 85 C 61 MSP432P401R MSP432P401M www ti com SLAS826F MARCH 2015 REVISED MARCH 2017 Submit Documentation Feedback Product Folder Links MSP432P401R MSP432P401M Specifications Copyright 2015 2017 Texas Instruments Incorporated 5 25 5 1 Typical Characteristics Normal Drive I O Outputs at 3 0 V and 2 2 V VCC 2 2 V P7 0 Figure 5...

Page 62: ...3 0 6 0 9 1 2 1 5 1 8 2 1 2 4 2 7 3 0 20 40 60 80 100 120 140 160 D009 TA 25 C TA 85 C 62 MSP432P401R MSP432P401M SLAS826F MARCH 2015 REVISED MARCH 2017 www ti com Submit Documentation Feedback Product Folder Links MSP432P401R MSP432P401M Specifications Copyright 2015 2017 Texas Instruments Incorporated 5 25 5 2 Typical Characteristics High Drive I O Outputs at 3 0 V and 2 2 V VCC 2 2 V P2 1 Figur...

Page 63: ... MSP432P401R MSP432P401M www ti com SLAS826F MARCH 2015 REVISED MARCH 2017 Submit Documentation Feedback Product Folder Links MSP432P401R MSP432P401M Specifications Copyright 2015 2017 Texas Instruments Incorporated 5 25 5 3 Typical Characteristics Pin Oscillator Frequency One output active at a time VCC 3 0 V Figure 5 27 Load Capacitance vs Pin Oscillator Frequency One output active at a time VCC...

Page 64: ...DC14PWRMD 2 1 62 3 7 V AVCC Analog supply voltage AVCC and DVCC are connected together AVSS and DVSS are connected together V AVSS V DVSS 0 V ADC14PWRMD 0 1 8 3 7 V V Ax Analog input voltage range 1 All ADC analog input pins Ax 0 AVCC V VCM Input common mode range All ADC analog input pins Ax ADC14DIF 1 0 VREF 2 VREF V I ADC14 single ended mode Operating supply current into AVCC and DVCC terminals...

Page 65: ...V 0 128 25 MHz ADC14PWRMD 2 1 62 V to 3 7 V 0 128 5 75 NCONVERT Clock cycles for conversion ADC14RES 11 16 cycles ADC14RES 10 14 ADC14RES 01 11 ADC14RES 00 9 tADC14ON Turnon settling time of ADC See 2 1 5 µs tSample Sampling time 3 4 RS 200 Ω Cpext 10 pF RI 1 kΩ CI 15 pF Cpint 5 pF 0 215 µs Table 5 28 lists the linearity parameters of the ADC 1 Minimum reference voltage of 1 45 V is necessary to m...

Page 66: ...20 kHz input sine DC DC based operation 62 70 1 Msps ADC14DIF 1 ADC14VRSEL 0xE 2 5 V reference 20 kHz input sine 79 81 ENOB 2 Effective number of bits 1 Msps ADC14DIF 0 ADC14VRSEL 0xE 2 5 V reference 20 kHz input sine LDO based operation 11 5 11 8 bit 1 Msps ADC14DIF 0 ADC14VRSEL 0xE 2 5 V reference 20 kHz input sine DC DC based operation 10 11 3 1 Msps ADC14DIF 1 ADC14VRSEL 0xE 2 5 V reference 20...

Page 67: ...NSOR and VSENSOR can be computed from the calibration values for higher accuracy 3 The typical equivalent impedance of the sensor is 250 kΩ The sample time required includes the sensor on time tSENSOR on 4 The on time tV1 2 on is included in the sampling time tV 1 2 sample No additional on time is needed Table 5 30 14 Bit ADC Temperature Sensor and Built In V1 2 over recommended ranges of supply v...

Page 68: ...nearity parameters 2 Two decoupling capacitors 5 µF and 50 nF should be connected to VeREF terminal to decouple the dynamic current required for an external reference source if it is used for the ADC14 Also see the MSP432P4xx SimpleLink Microcontrollers Technical Reference Manual Table 5 32 14 Bit ADC External Reference over recommended ranges of supply voltage and operating free air temperature u...

Page 69: ...gle Ended Differential Ended 69 MSP432P401R MSP432P401M www ti com SLAS826F MARCH 2015 REVISED MARCH 2017 Submit Documentation Feedback Product Folder Links MSP432P401R MSP432P401M Specifications Copyright 2015 2017 Texas Instruments Incorporated 5 25 6 1 Typical Characteristics of ADC typical characteristics at 3 V 25 C and 1 Msps sampling rate of ADC unless otherwise specified VRSEL 14 VREF 2 5 ...

Page 70: ... 1 5 2 D055 ADC Output Code Typical Integral Nonlinearilty LSB 0 2048 4096 6144 8192 10240 12288 14336 16384 2 1 5 1 0 5 0 0 5 1 1 5 2 D056 70 MSP432P401R MSP432P401M SLAS826F MARCH 2015 REVISED MARCH 2017 www ti com Submit Documentation Feedback Product Folder Links MSP432P401R MSP432P401M Specifications Copyright 2015 2017 Texas Instruments Incorporated VRSEL 1 VREF 2 5 V Input Mode Single Ended...

Page 71: ... 75 0 5 0 25 0 0 25 0 5 0 75 1 D061 ADC Output Code Typical Differential Nonlinearilty LSB 0 2048 4096 6144 8192 10240 12288 14336 16384 1 0 75 0 5 0 25 0 0 25 0 5 0 75 1 D062 71 MSP432P401R MSP432P401M www ti com SLAS826F MARCH 2015 REVISED MARCH 2017 Submit Documentation Feedback Product Folder Links MSP432P401R MSP432P401M Specifications Copyright 2015 2017 Texas Instruments Incorporated VRSEL ...

Page 72: ...1R MSP432P401M SLAS826F MARCH 2015 REVISED MARCH 2017 www ti com Submit Documentation Feedback Product Folder Links MSP432P401R MSP432P401M Specifications Copyright 2015 2017 Texas Instruments Incorporated fin 20 kHz VRSEL 1 VREF 2 5 V SINAD 69 dB THD 86 dB Input Mode Single Ended Figure 5 47 Power vs Input Frequency fin 20 kHz VRSEL 1 VREF 2 5 V SINAD 74 dB THD 91 dB Input Mode Differential Figur...

Page 73: ...ingle Ended Differential Ended Reference Voltage V Effective Number of Bits 1 1 25 1 5 1 75 2 2 25 2 5 2 75 9 10 11 12 13 14 15 D074 Single Ended Differential Ended 73 MSP432P401R MSP432P401M www ti com SLAS826F MARCH 2015 REVISED MARCH 2017 Submit Documentation Feedback Product Folder Links MSP432P401R MSP432P401M Specifications Copyright 2015 2017 Texas Instruments Incorporated fin 20 kHz VRSEL ...

Page 74: ...Differential Ended Temperature C Effective Number of Bits 60 40 20 0 20 40 60 80 100 10 11 12 13 14 15 16 D078 Single Ended Differential Ended 74 MSP432P401R MSP432P401M SLAS826F MARCH 2015 REVISED MARCH 2017 www ti com Submit Documentation Feedback Product Folder Links MSP432P401R MSP432P401M Specifications Copyright 2015 2017 Texas Instruments Incorporated fin 20 kHz VRSEL 14 VREF 2 5 V Figure 5...

Page 75: ...al Nonlinearity LSB 60 40 20 0 20 40 60 80 100 2 1 5 1 0 5 0 0 5 1 1 5 2 D082 Maximum INL Minimum INL 75 MSP432P401R MSP432P401M www ti com SLAS826F MARCH 2015 REVISED MARCH 2017 Submit Documentation Feedback Product Folder Links MSP432P401R MSP432P401M Specifications Copyright 2015 2017 Texas Instruments Incorporated VRSEL 14 VREF 2 5 V Input Mode Single Ended Figure 5 61 INL vs Temperature VRSEL...

Page 76: ...0 5 D086 76 MSP432P401R MSP432P401M SLAS826F MARCH 2015 REVISED MARCH 2017 www ti com Submit Documentation Feedback Product Folder Links MSP432P401R MSP432P401M Specifications Copyright 2015 2017 Texas Instruments Incorporated VRSEL 14 VREF 2 5 V Input Mode Single Ended Figure 5 65 Offset Voltage vs Temperature VRSEL 14 VREF 2 5 V Input Mode Differential Figure 5 66 Offset Voltage vs Temperature V...

Page 77: ...or 2 5 V 2 8 IREF Operating supply current into AVCC terminal 1 REFON 1 3 V 15 20 µA IO VREF VREF maximum load current VREF terminal REFVSEL 0 1 3 AVCC AVCC min for each reference level REFON REFOUT 1 1000 10 µA IL VREF Load current regulation VREF terminal REFVSEL 0 1 3 I VREF 10 µA or 1000 µA AVCC AVCC min for each reference level REFON REFOUT 1 2500 µV mA CVREF Capacitance at VREF VREF terminal...

Page 78: ... 0 CEON 0 2 2 V 3 V 25 35 µA CEREFACC 1 CEREFLx 01 CERSx 10 REFON 0 CEON 0 2 2 V 3 V 10 15 VREF Reference voltage level CERSx 11 CEREFLx 01 CEREFACC 0 1 62 V 1 17 1 2 1 23 V CERSx 11 CEREFLx 10 CEREFACC 0 2 2 V 1 95 2 0 2 05 CERSx 11 CEREFLx 11 CEREFACC 0 2 7 V 2 40 2 5 2 60 CERSx 11 CEREFLx 01 CEREFACC 1 1 62 V 1 15 1 2 1 23 CERSx 11 CEREFLx 10 CEREFACC 1 2 2 V 1 92 2 0 2 05 CERSx 11 CEREFLx 11 C...

Page 79: ...WRMD 00 CEREFLx 10 CERSx 11 REFON 0 Overdrive 20 mV 90 120 µs CEON 0 to 1 CEPWRMD 01 CEREFLx 10 CERSx 11 REFON 0 Overdrive 20 mV 90 120 CEON 0 to 1 CEPWRMD 10 CEREFLx 10 CERSx 11 REFON 0 Overdrive 20 mV 90 120 CEON 0 to 1 CEPWRMD 00 CEREFLx 10 CERSx 10 REFON 0 CEREF0 1 0x0F Overdrive 20 mV 90 180 CEON 0 to 1 CEPWRMD 01 CEREFLx 10 CERSx 10 REFON 0 CEREF0 1 0x0F Overdrive 20 mV 90 180 CEON 0 to 1 CE...

Page 80: ...the UART receive input UCxRX that are shorter than the UART receive deglitch time are suppressed Thus the selected deglitch time can limit the maximum useable baud rate To ensure that pulses are correctly recognized their duration should exceed the maximum specification of the deglitch time Table 5 36 eUSCI UART Mode Switching Characteristics over recommended ranges of supply voltage and operating...

Page 81: ... on the SIMO output can become invalid before the output changing clock edge observed on UCLK See the timing diagrams in Figure 5 69 and Figure 5 70 Table 5 38 eUSCI SPI Master Mode over recommended ranges of supply voltage and operating free air temperature unless otherwise noted 1 PARAMETER TEST CONDITIONS VCORE VCC MIN MAX UNIT tSTE LEAD STE lead time STE active to clock UCSTEM 1 UCMODEx 01 or ...

Page 82: ... 0 CKPL 1 tLOW HIGH tLOW HIGH 1 fUCxCLK STE tSTE LEAD tSTE LAG UCMODEx 01 UCMODEx 10 tHD MO tSTE ACC tSTE DIS 82 MSP432P401R MSP432P401M SLAS826F MARCH 2015 REVISED MARCH 2017 www ti com Submit Documentation Feedback Product Folder Links MSP432P401R MSP432P401M Specifications Copyright 2015 2017 Texas Instruments Incorporated Figure 5 69 SPI Master Mode CKPH 0 Figure 5 70 SPI Master Mode CKPH 1 ...

Page 83: ...ng diagrams in Figure 5 71 and Figure 5 72 3 Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge See the timing diagrams in Figure 5 71 and Figure 5 72 Table 5 39 eUSCI SPI Slave Mode over recommended ranges of supply voltage and operating free air temperature unless otherwise noted 1 PARAMETER TEST CONDITIONS VCC MIN MAX UNIT tSTE LEAD STE lead time STE a...

Page 84: ...TE ACC STE tSTE LEAD tSTE LAG UCMODEx 01 UCMODEx 10 84 MSP432P401R MSP432P401M SLAS826F MARCH 2015 REVISED MARCH 2017 www ti com Submit Documentation Feedback Product Folder Links MSP432P401R MSP432P401M Specifications Copyright 2015 2017 Texas Instruments Incorporated Figure 5 72 SPI Slave Mode CKPH 1 ...

Page 85: ... the eUSCI in I2 C mode Table 5 41 eUSCI I2 C Mode over recommended ranges of supply voltage and operating free air temperature unless otherwise noted see Figure 5 73 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tHD STA Hold time repeated START fSCL 100 kHz 5 5 µs fSCL 400 kHz 1 5 fSCL 1 MHz 0 6 tSU STA Setup time for a repeated START fSCL 100 kHz 5 5 µs fSCL 400 kHz 1 5 fSCL 1 MHz 0 6 tHD DAT Data ...

Page 86: ... noted PARAMETER TEST CONDITIONS VCORE VCC MIN MAX UNIT fTA Timer_A input clock frequency Internal SMCLK External TACLK Duty cycle 50 10 1 2 V 12 MHz 1 4 V 24 tTA cap Timer_A capture timing All capture inputs Minimum pulse duration required for capture 20 ns Table 5 43 lists the characteristics of Timer32 1 Timer32 operates on the same clock as the Cortex M4 CPU Table 5 43 Timer32 over recommended...

Page 87: ...AX_ERS for the specific erase or program endurance and the total number of sectors in the flash main memory Table 5 45 Flash Operations Using MSP432 Peripheral Driver Libraries 1 over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPGM_API Word Program time for 32 bit data using ROM_FlashCtl_programMemory AP...

Page 88: ...e AUTO_PRE 0 AUTO_PST 1 65 µs AUTO_PRE 1 AUTO_PST 1 85 tERS Time for sector erase or mass erase 9 ms NMAX_PGM Maximum number of pulses to complete program operation 5 NMAX_ERS Maximum number of pulses to complete erase operation Number of erase or program cycles 1k 34 Number of erase or program cycles 1k and 20k 334 Table 5 47 lists the characteristics of the SRAM Table 5 47 SRAM over recommended ...

Page 89: ...5 48 JTAG over recommended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER MIN TYP MAX UNIT fTCK TCK clock frequency 0 10 MHz tTCK TCK clock period 100 ns tTCK_LOW TCK clock low time tTCK 2 ns tTCK_HIGH TCK clock high time tTCK 2 ns tTCK_RISE TCK rise time 0 10 ns tTCK_FALL TCK fall time 0 10 ns tTMS_SU TMS setup time to TCK rise 30 ns tTMS_HLD TMS hold...

Page 90: ...gle precision floating point module supporting add subtract multiply divide accumulate and square root operations It also provides conversion between fixed point and floating point data formats and floating point constant instructions 6 2 2 Memory Protection Unit The Cortex M4 processor on the MSP432P401x MCUs includes a tightly coupled memory protection unit MPU that supports up to eight protecti...

Page 91: ...erial Wire Viewer SWV can export a stream of software generated messages data trace and profiling information through a single pin NOTE For detailed specifications and information on the programmer s model for the Cortex M4 CPU and the associated peripherals mentioned throughout Section 6 2 see the appropriate reference manual at www arm com 6 3 Memory Map The device supports a 4GB address space t...

Page 92: ...flash memory region This region is further divided into different types of flash memory regions which are explained in Section 6 4 1 6 3 1 2 SRAM Region The 1MB region from 0x0100_0000 to 0x010F_FFFF is defined as the SRAM region This region is also aliased in the SRAM zone of the device thereby allowing efficient access to the SRAM both for instruction fetches and data reads See Section 6 4 2 for...

Page 93: ...the Code zone of the device thereby allowing efficient access to the SRAM both for instruction fetches and data reads See Section 6 4 2 for details about the SRAM 6 3 2 2 SRAM Bit Band Alias Region The 32MB region from 0x2200_0000 through 0x23FF_FFFF forms the bit band alias region for the 1 MB SRAM region Bit banding is a feature of the Cortex M4 processor and allows the application to set or cle...

Page 94: ...ls in the REMARKS column If a peripheral is listed as N A for a particular device treat the corresponding address space as reserved NOTE Peripherals that are marked as 16 bit should be accessed through byte or half word size read or write only Any 32 bit access to these peripherals results in a bus error response Table 6 1 Peripheral Address Offsets ADDRESS RANGE PERIPHERAL TABLE REMARKS 0x4000_00...

Page 95: ...h I O 1 Table 6 24 16 bit peripheral 0x4000_5C00 0x4000_8FFF Reserved Read only always reads 0h 0x4000_9000 0x4000_BFFF Reserved Read only always reads 0h 0x4000_C000 0x4000_CFFF Timer32 Table 6 25 0x4000_D000 0x4000_DFFF Reserved Read only always reads 0h 0x4000_E000 0x4000_FFFF DMA Table 6 26 0x4001_0000 0x4001_03FF PCM Table 6 27 0x4001_0400 0x4001_07FF CS Table 6 28 0x4001_0800 0x4001_0FFF PSS...

Page 96: ... Control TA2CTL 00h Timer_A2 Capture Compare Control 0 TA2CCTL0 02h Timer_A2 Capture Compare Control 1 TA2CCTL1 04h Timer_A2 Capture Compare Control 2 TA2CCTL2 06h Timer_A2 Capture Compare Control 3 TA2CCTL3 08h Timer_A2 Capture Compare Control 4 TA2CCTL4 0Ah Timer_A2 Counter TA2R 10h Timer_A2 Capture Compare 0 TA2CCR0 12h Timer_A2 Capture Compare 1 TA2CCR1 14h Timer_A2 Capture Compare 2 TA2CCR2 1...

Page 97: ...V 1Eh Table 6 7 eUSCI_A1 Registers Base Address 0x4000_1400 REGISTER NAME ACRONYM OFFSET eUSCI_A1 Control Word 0 UCA1CTLW0 00h eUSCI_A1 Control Word 1 UCA1CTLW1 02h eUSCI_A1 Baud Rate Control UCA1BRW 06h eUSCI_A1 Modulation Control UCA1MCTLW 08h eUSCI_A1 Status UCA1STATW 0Ah eUSCI_A1 Receive Buffer UCA1RXBUF 0Ch eUSCI_A1 Transmit Buffer UCA1TXBUF 0Eh eUSCI_A1 Auto Baud Rate Control UCA1ABCTL 10h e...

Page 98: ...trol Word UCB0BRW 06h eUSCI_B0 Status Word UCB0STATW 08h eUSCI_B0 Byte Counter Threshold UCB0TBCNT 0Ah eUSCI_B0 Receive Buffer UCB0RXBUF 0Ch eUSCI_B0 Transmit Buffer UCB0TXBUF 0Eh eUSCI_B0 I2C Own Address 0 UCB0I2COA0 14h eUSCI_B0 I2C Own Address 1 UCB0I2COA1 16h eUSCI_B0 I2C Own Address 2 UCB0I2COA2 18h eUSCI_B0 I2C Own Address 3 UCB0I2COA3 1Ah eUSCI_B0 Received Address UCB0ADDRX 1Ch eUSCI_B0 Add...

Page 99: ...eUSCI_B2 I2C Own Address 1 UCB2I2COA1 16h eUSCI_B2 I2C Own Address 2 UCB2I2COA2 18h eUSCI_B2 I2C Own Address 3 UCB2I2COA3 1Ah eUSCI_B2 Received Address UCB2ADDRX 1Ch eUSCI_B2 Address Mask UCB2ADDMASK 1Eh eUSCI_B2 I2C Slave Address UCB2I2CSA 20h eUSCI_B2 Interrupt Enable UCB2IE 2Ah eUSCI_B2 Interrupt Flag UCB2IFG 2Ch eUSCI_B2 Interrupt Vector UCB2IV 2Eh Table 6 13 eUSCI_B3 Registers Base Address 0x...

Page 100: ...h Comparator_E1 Control 3 CE1CTL3 06h Comparator_E1 Interrupt CE1INT 0Ch Comparator_E1 Interrupt Vector Word CE1IV 0Eh Table 6 17 AES256 Registers Base Address 0x4000_3C00 REGISTER NAME ACRONYM OFFSET AES Accelerator Control 0 AESACTL0 00h AES Accelerator Control 1 AESACTL1 02h AES Accelerator Status AESASTAT 04h AES Accelerator Key AESAKEY 06h AES Accelerator Data In AESADIN 08h AES Accelerator D...

Page 101: ...l Time Clock Day of Week Day of Month Alarm RTCADOWDAY 1Ah Binary to BCD Conversion RTCBIN2BCD 1Ch BCD to Binary Conversion RTCBCD2BIN 1Eh Table 6 20 WDT_A Registers Base Address 0x4000_4800 REGISTER NAME ACRONYM OFFSET Watchdog Timer Control WDTCTL 0Ch Table 6 21 Port Registers Base Address 0x4000_4C00 REGISTER NAME ACRONYM OFFSET Port 1 Input P1IN 000h Port 2 Input P2IN 001h Port 1 Output P1OUT ...

Page 102: ...terrupt Edge Select P4IES 039h Port 3 Interrupt Enable P3IE 03Ah Port 4 Interrupt Enable P4IE 03Bh Port 3 Interrupt Flag P3IFG 03Ch Port 4 Interrupt Flag P4IFG 03Dh Port 4 Interrupt Vector P4IV 03Eh Port 5 Input P5IN 040h Port 6 Input P6IN 041h Port 5 Output P5OUT 042h Port 6 Output P6OUT 043h Port 5 Direction P5DIR 044h Port 6 Direction P6DIR 045h Port 5 Resistor Enable P5REN 046h Port 6 Resistor...

Page 103: ...rt 7 Interrupt Flag P7IFG 07Ch Port 8 Interrupt Flag P8IFG 07Dh Port 8 Interrupt Vector P8IV 07Eh Port 9 Input P9IN 080h Port 10 Input P10IN 081h Port 9 Output P9OUT 082h Port 10 Output P10OUT 083h Port 9 Direction P9DIR 084h Port 10 Direction P10DIR 085h Port 9 Resistor Enable P9REN 086h Port 10 Resistor Enable P10REN 087h Port 9 Select 0 P9SEL0 08Ah Port 10 Select 0 P10SEL0 08Bh Port 9 Select 1 ...

Page 104: ...ort Mapping P3 6 P3MAP6 1Eh Port Mapping P3 7 P3MAP7 1Fh Port Mapping P7 0 P7MAP0 38h Port Mapping P7 1 P7MAP1 39h Port Mapping P7 2 P7MAP2 3Ah Port Mapping P7 3 P7MAP3 3Bh Port Mapping P7 4 P7MAP4 3Ch Port Mapping P7 5 P7MAP5 3Dh Port Mapping P7 6 P7MAP6 3Eh Port Mapping P7 7 P7MAP7 3Fh Table 6 23 Capacitive Touch I O 0 Registers Base Address 0x4000_5400 REGISTER NAME ACRONYM OFFSET Capacitive To...

Page 105: ...hannel 7 Source Configuration DMA_CH7_SRCCFG 02Ch Interrupt 1 Source Channel Configuration DMA_INT1_SRCCFG 100h Interrupt 2 Source Channel Configuration DMA_INT2_SRCCFG 104h Interrupt 3 Source Channel Configuration DMA_INT3_SRCCFG 108h Interrupt 0 Source Channel Flag DMA_INT0_SRCFLG 110h Interrupt 0 Source Channel Clear Flag DMA_INT0_CLRFLG 114h Status DMA_STAT 1000h Configuration DMA_CFG 1004h Ch...

Page 106: ...SCTL0 04h Interrupt Enable PSSIE 34h Interrupt Flag PSSIFG 38h Clear Interrupt Flag PSSCLRIFG 3Ch Table 6 30 FLCTL Registers Base Address 0x4001_1000 REGISTER NAME ACRONYM OFFSET Power Status FLCTL_POWER_STAT 000h Bank 0 Read Control FLCTL_BANK0_RDCTL 010h Bank 1 Read Control FLCTL_BANK1_RDCTL 014h Read Burst Compare Control and Status FLCTL_RDBRST_CTLSTAT 020h Read Burst Compare Start Address FLC...

Page 107: ...n FLCTL_BANK1_MAIN_WEPROT 0C4h Benchmark Control and Status FLCTL_BMRK_CTLSTAT 0D0h Benchmark Instruction Fetch Count FLCTL_BMRK_IFETCH 0D4h Benchmark Data Read Count FLCTL_BMRK_DREAD 0D8h Benchmark Count Compare FLCTL_BMRK_CMP 0DCh Interrupt Flag FLCTL_IFG 0F0h Interrupt Enable FLCTL_IE 0F4h Clear Interrupt Flag FLCTL_CLRIFG 0F8h Set Interrupt Flag FLCTL_SETIFG 0FCh Read Timing Control FLCTL_READ...

Page 108: ...L19 64h Memory Control 20 ADC14MCTL20 68h Memory Control 21 ADC14MCTL21 6Ch Memory Control 22 ADC14MCTL22 70h Memory Control 23 ADC14MCTL23 74h Memory Control 24 ADC14MCTL24 78h Memory Control 25 ADC14MCTL25 7Ch Memory Control 26 ADC14MCTL26 80h Memory Control 27 ADC14MCTL27 84h Memory Control 28 ADC14MCTL28 88h Memory Control 29 ADC14MCTL29 8Ch Memory Control 30 ADC14MCTL30 90h Memory Control 31 ...

Page 109: ...FGR0 144h Interrupt Flag 1 ADC14IFGR1 148h Clear Interrupt Flag 0 ADC14CLRIFGR0 14Ch Clear Interrupt Flag 1 ADC14CLRIFGR1 150h Interrupt Vector ADC14IV 154h 6 3 3 2 Peripheral Bit Band Alias Region The 32MB region from 0x4200_0000 through 0x43FF_FFFF forms the bit band alias region for the 1MB peripheral region Bit banding is a feature of the Cortex M4 processor and allows the application to set o...

Page 110: ...FFF TPIU External PPB 0xE004_1000 0xE004_1FFF Reserved External PPB 0xE004_2000 0xE004_23FF Reset Controller see Table 6 33 External PPB 0xE004_2400 0xE004_2FFF Reserved External PPB 0xE004_3000 0xE004_33FF System Controller see Table 6 34 External PPB 0xE004_3400 0xE004_3FFF Reserved External PPB 0xE004_4000 0xE004_43FF System Controller External PPB 0xE004_4400 0xE00F_EFFF Reserved External PPB ...

Page 111: ...ide Request 0 SYS_BOOTOVER_REQ0 1004h Boot Override Request 1 SYS_BOOTOVER_REQ1 1008h Boot Override Acknowledge SYS_BOOTOVER_ACK 100Ch Reset Request SYS_RESET_REQ 1010h Reset Status and Override SYS_RESET_STATOVER 1014h System Status SYS_SYSTEM_STAT 1020h 6 4 Memories on the MSP432P401x The MSP432P401x MCUs include flash memory and SRAM for general application purposes In addition the devices incl...

Page 112: ...descriptor TLV is factory configured for protection against write and erase operations Table 6 35 Flash Information Memory Regions REGION ADDRESS RANGE CONTENTS WRITE AND ERASE PROTECTED Bank 0 Sector 0 0x0020_0000 0x0020_0FFF Flash Boot override Mailbox No Bank 0 Sector 1 0x0020_1000 0x0020_1FFF Device Descriptor TLV Yes Bank 1 Sector 0 0x0020_2000 0x0020_2FFF TI BSL No Bank 1 Sector 1 0x0020_300...

Page 113: ...nge is effected See the electrical specification for details on flash wait state requirements 6 4 2 SRAM The MSP432P401x MCUs support up to 64KB of SRAM with the rest of the 1MB SRAM region reserved The SRAM is aliased in both Code and SRAM zones This enables fast single cycle execution of code from the SRAM as the Cortex M4 processor pipelines instruction fetches to memory zones other than the Co...

Page 114: ...ubset of the enabled banks For example the application may need 32KB of SRAM for its processing needs four banks are kept enabled However of these four banks only one bank may contain critical data that must be retained in LPM3 or LPM4 while the rest are powered off completely to minimize power consumption Bank 0 of SRAM is always retained and cannot be powered down Therefore it also operates up a...

Page 115: ...USCI_B2 RX1 eUSCI_B1 RX2 eUSCI_B0 RX3 TA3CCR2 ADC14 NOTE Any source marked as Reserved is unused It may be used for software controlled DMA tasks but typically it is reserved for enhancement purposes on future devices 6 5 2 DMA Completion Interrupts In the case of the ARM µDMA controller it is usually the responsibility of software to maintain a list of channels that have completed their operation...

Page 116: ...Priority FLASH MEMORY ROM SRAM PERIPHERALS ICODE 3 2 4 N A DCODE 2 1 1 2 N A SBUS N A N A 3 2 DMA 1 2 N A 1 3 1 1 A reserved memory region returns 0h on reads and instruction fetches Writes to this region are ignored 2 If the user memory address is part of a secure region this access returns an error if it is initiated by an unauthorized source For more details see Configuring Security and Bootloa...

Page 117: ...so be mapped to the system NMI See the MSP432P4xx SimpleLink Microcontrollers Technical Reference Manual for more details 6 7 Interrupts The Cortex M4 processor on MSP432P401x MCUs implements an NVIC with 64 external interrupt lines and 8 levels of priority From an application perspective the interrupt sources at the device level are divided into two classes the NMI and the User Interrupts Interna...

Page 118: ...RT or SPI mode TX RX and Status Flags INTISR 17 eUSCI_A1 UART or SPI mode TX RX and Status Flags INTISR 18 eUSCI_A2 UART or SPI mode TX RX and Status Flags INTISR 19 eUSCI_A3 UART or SPI mode TX RX and Status Flags INTISR 20 eUSCI_B0 SPI or I2 C mode TX RX and Status Flags I2 C in multiple slave mode INTISR 21 eUSCI_B1 SPI or I2 C mode TX RX and Status Flags I2 C in multiple slave mode INTISR 22 e...

Page 119: ...ut the write and wait for a few cycles before exiting the ISR Alternatively the application can do an explicit read to ensure that the flag is cleared before exiting the ISR 6 8 System Control System Control comprises the modules that govern the overall behavior of the device including power management operating modes clocks reset handling and user configuration settings 6 8 1 Device Resets The MS...

Page 120: ...32P4xx SimpleLink Microcontrollers Technical Reference Manual 1 The WDT_A generated resets can be mapped either as a Hard Reset or a Soft Reset 2 The FLCTL can generate a reset if a voltage anomaly is detected that can corrupt only flash reads and not the rest of the system 3 Reserved indicates that this source of Hard Reset is currently unused and left for future expansion 4 The CS is technically...

Page 121: ...sion Table 6 41 MSP432P401x Soft Reset Sources RESET SOURCE NUMBER SOURCE 0 CPU LOCKUP Condition LOCKUP output of Cortex M4 1 WDT_A Time out 1 2 WDT_A Password Violation 1 3 Reserved 2 4 Reserved 2 5 Reserved 2 6 Reserved 2 7 Reserved 2 8 Reserved 2 9 Reserved 2 10 Reserved 2 11 Reserved 2 12 Reserved 2 13 Reserved 2 14 Reserved 2 15 Reserved 2 NOTE To support and enhance debug of reset conditions...

Page 122: ...witching between the modes This is controlled by the application which can choose modes to meet its power and performance requirements Table 6 42 lists the operating modes of the device Table 6 42 MSP432P401x Operating Modes OPERATING MODE DESCRIPTION AM_LDO_VCORE0 LDO based active mode normal performance core voltage level 0 LPM0_LDO_VCORE0 Same as above except that CPU is OFF no code execution A...

Page 123: ... The REFO can also be programmed to generate a 128 kHz clock 6 8 4 6 Module Oscillator MODOSC The MODOSC is an internal clock source that has a very low latency wake up time It is factory calibrated to a frequency of 25 MHz The MODOSC is typically used to supply a clock on request to different modules It can be used as a clock source for ADC operation at 1 Msps sampling rate 6 8 4 7 System Oscilla...

Page 124: ...rogrammable pullup or pulldown on all ports Edge selectable interrupt capability is available on ports P1 through P6 Wake up capability from LPM3 LPM4 LPM3 5 and LPM4 5 modes on ports P1 through P6 Read and write access to port control registers is supported by all instructions Ports can be accessed byte wise or in pairs 16 bit widths Capacitive touch functionality is supported on all pins of port...

Page 125: ...led by eUSCI 9 PM_UCA1RXD eUSCI_A1 UART RXD direction controlled by eUSCI Input PM_UCA1SOMI eUSCI_A1 SPI slave out master in direction controlled by eUSCI 10 PM_UCA1TXD eUSCI_A1 UART TXD direction controlled by eUSCI Output PM_UCA1SIMO eUSCI_A1 SPI slave in master out direction controlled by eUSCI 11 PM_UCA2STE eUSCI_A2 SPI slave transmit enable direction controlled by eUSCI 12 PM_UCA2CLK eUSCI_A2...

Page 126: ...3 1 PM_TA0 3 TA0 CCR3 capture input CCI3A TA0 CCR3 compare output Out3 P2 7 PM_TA0 4 1 PM_TA0 4 TA0 CCR4 capture input CCI4A TA0 CCR4 compare output Out4 P3 0 PM_UCA2STE PM_UCA2STE eUSCI_A2 SPI slave transmit enable direction controlled by eUSCI P3 1 PM_UCA2CLK PM_UCA2CLK eUSCI_A2 clock input output direction controlled by eUSCI P3 2 PM_UCA2RXD PM_UCA2SOMI PM_UCA2RXD PM_UCA2SOMI eUSCI_A2 UART RXD ...

Page 127: ... or internal signal that sources the clocks and or triggers into the Timer The default assumption is that these are pins unless specifically marked as internal Nomenclature used for internal signals is as follows CxOUT output from Comparator x TAx_Cy Output from Timer x Capture Compare module y The second column lists the input signals of the Timer module The third column lists the submodule of th...

Page 128: ...ACLK Timer N A N A ACLK internal ACLK SMCLK internal SMCLK C0OUT internal INCLK P7 3 PM_TA0 0 CCI0A CCR0 TA0 P7 3 PM_TA0 0 TA0_C0 internal DVSS CCI0B DVSS GND DVCC VCC P2 4 PM_TA0 1 CCI1A CCR1 TA1 P2 4 PM_TA0 1 ACLK internal CCI1B TA0_C1 internal DVSS GND ADC14 internal DVCC VCC ADC14SHSx 1 P2 5 PM_TA0 2 CCI2A CCR2 TA2 P2 5 PM_TA0 2 C0OUT internal CCI2B TA0_C2 internal DVSS GND ADC14 internal DVCC...

Page 129: ...al ACLK SMCLK internal SMCLK C1OUT internal INCLK P8 0 UCB3STE TA1 0 C0 1 CCI0A CCR0 TA0 P8 0 UCB3STE TA1 0 C0 1 TA1_C0 internal DVSS CCI0B DVSS GND DVCC VCC P7 7 PM_TA1 1 C0 2 CCI1A CCR1 TA1 P7 7 PM_TA1 1 C0 2 TA1_C1 internal ADC14 internal ADC14SHSx 3 ACLK internal CCI1B DVSS GND DVCC VCC P7 6 PM_TA1 2 C0 3 CCI2A CCR2 TA2 P7 6 PM_TA1 2 C0 3 TA1_C2 internal ADC14 internal ADC14SHSx 4 C0OUT intern...

Page 130: ...LK P8 1 UCB3CLK TA2 0 C0 0 CCI0A CCR0 TA0 P8 1 UCB3CLK TA2 0 C0 0 TA2_C0 internal DVSS CCI0B DVSS GND DVCC VCC P5 6 TA2 1 VREF VeREF C1 7 CCI1A CCR1 TA1 P5 6 TA2 1 VREF VeREF C1 7 TA2_C1 internal ADC14 internal ADC14SHSx 5 ACLK internal CCI1B DVSS GND DVCC VCC P5 7 TA2 2 VREF VeREF C1 6 CCI2A CCR2 TA2 P5 7 TA2 2 VREF VeREF C1 6 TA2_C2 internal ADC14 internal ADC14SHSx 6 C0OUT internal CCI2B DVSS G...

Page 131: ...is an ARM dual 32 bit timer module It contains two 32 bit timers each of which can be configured as two independent 16 bit timers The two timers can generate independent events or a combined event which can be processed according to application requirements Timer32 runs out of the same clock as the Cortex M4 CPU 6 9 5 Enhanced Universal Serial Communication Interface eUSCI The eUSCI modules are us...

Page 132: ...tion This reset can be configured to generate either a Hard Reset or a Soft Reset into the system See the MSP432P4xx SimpleLink Microcontrollers Technical Reference Manual for more details The WDT should typically be configured to generate a Hard reset into the system A Soft reset resets the CPU but leaves the rest of the system and peripherals unaffected As a result if the WDT is configured to ge...

Page 133: ... table Table 6 52 ADC14 Channel Mapping on 100 Pin PZ Devices ADC14 CHANNEL EXTERNAL CHANNEL SOURCE CONTROL BIT 0 INTERNAL CHANNEL SOURCE CONTROL BIT 1 1 CONTROL BIT 2 Channel 23 A23 Battery Monitor ADC14BATMAP Channel 22 A22 Temperature Sensor ADC14TCMAP Channel 21 A21 N A Reserved ADC14CH0MAP Channel 20 A20 N A Reserved ADC14CH1MAP Channel 19 A19 N A Reserved ADC14CH2MAP Channel 18 A18 N A Reser...

Page 134: ...t can be used by the various analog peripherals in the device The reference voltage from REF_A can also be switched onto a device pin for external use 6 9 11 CRC32 The CRC32 module produces a signature based on a sequence of entered data values and can be used for data checking purposes It supports both a CRC32 and a CRC16 computation The CRC16 computation signature is based on the CRC16 CCITT sta...

Page 135: ... incrementing transmit and receive or continues its operation debug remains nonintrusive The registers of the peripheral remain accessible without regard to the values in the Peripheral Halt Control register 6 10 3 Bootloader BSL The BSL enables users to program flash or SRAM on the device using a UART or I2 C or SPI serial interface Access to the device memory through the BSL is protected by a us...

Page 136: ...ystem Controller SYSCTL chapter in the MSP432P4xx SimpleLink Microcontrollers Technical Reference Manual 6 11 Performance Benchmarks The MSP432P401xx MCUs achieve the following performance benchmarks under the given software configurations and profile configurations These performance benchmarks were measured with system supply voltage of 2 97 V at an ambient temperature of 25 C 6 11 1 ULPBench Per...

Page 137: ...and Version v1 0 Table 6 59 Profile Configuration CONFIGURATION DETAILS Active Power Mode Name Active Mode Active Mode Clock Configuration CPU 3 MHz Active Mode Voltage Integrity 1 62 V 6 11 3 DMIPS MHz Dhrystone 2 1 Performance 1 22 Table 6 60 shows the software configuration for this performance benchmark Table 6 61 shows the profile configuration Table 6 60 Software Configuration ITEMS DETAILS ...

Page 138: ...MARCH 2015 REVISED MARCH 2017 www ti com Submit Documentation Feedback Product Folder Links MSP432P401R MSP432P401M Detailed Description Copyright 2015 2017 Texas Instruments Incorporated 6 12 Input Output Diagrams 6 12 1 Port P1 P1 0 to P1 7 Input Output With Schmitt Trigger Figure 6 7 shows the port diagram Table 6 62 summarizes the selection of the pin functions Functional representation only F...

Page 139: ...0 UCA0STE 0 P1 0 I O I 0 O 1 0 0 UCA0STE X 2 0 1 N A 0 1 0 DVSS 1 N A 0 1 1 DVSS 1 P1 1 UCA0CLK 1 P1 1 I O I 0 O 1 0 0 UCA0CLK X 2 0 1 N A 0 1 0 DVSS 1 N A 0 1 1 DVSS 1 P1 2 UCA0RXD UCA0SOMI 2 P1 2 I O I 0 O 1 0 0 UCA0RXD UCA0SOMI X 2 0 1 N A 0 1 0 DVSS 1 N A 0 1 1 DVSS 1 P1 3 UCA0TXD UCA0SIMO 3 P1 3 I O I 0 O 1 0 0 UCA0TXD UCA0SIMO X 2 0 1 N A 0 1 0 DVSS 1 N A 0 1 1 DVSS 1 P1 4 UCB0STE 4 P1 4 I O...

Page 140: ...SP432P401R MSP432P401M Detailed Description Copyright 2015 2017 Texas Instruments Incorporated Table 6 62 Port P1 P1 0 to P1 7 Pin Functions continued PIN NAME P1 x x FUNCTION CONTROL BITS OR SIGNALS 1 P1DIR x P1SEL1 x P1SEL0 x P1 7 UCB0SOMI UCB0SCL 7 P1 7 I O I 0 O 1 0 0 UCB0SOMI UCB0SCL X 3 0 1 N A 0 1 0 DVSS 1 N A 0 1 1 DVSS 1 ...

Page 141: ...tion of the pin functions Table 6 63 Port P2 P2 0 to P2 3 Pin Functions PIN NAME P2 x x FUNCTION CONTROL BITS OR SIGNALS 1 P2DIR x P2SEL1 x P2SEL0 x P2MAPx P2 0 PM_UCA1STE 0 P2 0 I O I 0 O 1 0 0 X UCA1STE X 2 0 1 default N A 0 1 0 X DVSS 1 N A 0 1 1 X DVSS 1 P2 1 PM_UCA1CLK 1 P2 1 I O I 0 O 1 0 0 X UCA1CLK X 2 0 1 default N A 0 1 0 X DVSS 1 N A 0 1 1 X DVSS 1 P2 2 PM_UCA1RXD PM_U CA1SOMI 2 P2 2 I ...

Page 142: ...3 x x FUNCTION CONTROL BITS OR SIGNALS 1 P3DIR x P3SEL1 x P3SEL0 x P3MAPx P3 0 PM_UCA2STE 0 P3 0 I O I 0 O 1 0 0 X UCA2STE X 2 0 1 default N A 0 1 0 X DVSS 1 N A 0 1 1 X DVSS 1 P3 1 PM_UCA2CLK 1 P3 1 I O I 0 O 1 0 0 X UCA2CLK X 2 0 1 default N A 0 1 0 X DVSS 1 N A 0 1 1 X DVSS 1 P3 2 PM_UCA2RXD PM_U CA2SOMI 2 P3 2 I O I 0 O 1 0 0 X UCA2RXD UCA2SOMI X 2 0 1 default N A 0 1 0 X DVSS 1 N A 0 1 1 X DV...

Page 143: ...ments Incorporated Table 6 64 Port P3 P3 0 to P3 7 Pin Functions continued PIN NAME P3 x x FUNCTION CONTROL BITS OR SIGNALS 1 P3DIR x P3SEL1 x P3SEL0 x P3MAPx P3 6 PM_UCB2SIMO PM_ UCB2SDA 6 P3 6 I O I 0 O 1 0 0 X UCB2SIMO UCB2SDA X 3 0 1 default N A 0 1 0 X DVSS 1 N A 0 1 1 X DVSS 1 P3 7 PM_UCB2SOMI PM_ UCB2SCL 7 P3 7 I O I 0 O 1 0 0 X UCB2SOMI UCB2SCL X 3 0 1 default N A 0 1 0 X DVSS 1 N A 0 1 1 ...

Page 144: ... 6 7 shows the port diagram Table 6 65 summarizes the selection of the pin functions Table 6 65 Port P9 P9 4 to P9 7 Pin Functions PIN NAME P9 x x FUNCTION CONTROL BITS OR SIGNALS 1 P9DIR x P9SEL1 x P9SEL0 x P9 4 UCA3STE 2 4 P9 4 I O I 0 O 1 0 0 UCA3STE X 3 0 1 N A 0 1 0 DVSS 1 N A 0 1 1 DVSS 1 P9 5 UCA3CLK 2 5 P9 5 I O I 0 O 1 0 0 UCA3CLK X 3 0 1 N A 0 1 0 DVSS 1 N A 0 1 1 DVSS 1 P9 6 UCA3RXD UCA...

Page 145: ...hows the port diagram Table 6 66 summarizes the selection of the pin functions Table 6 66 Port P10 P10 0 to P10 3 Pin Functions PIN NAME P10 x x FUNCTION CONTROL BITS OR SIGNALS 1 P10DIR x P10SEL1 x P10SEL0 x P10 0 UCB3STE 2 0 P10 0 I O I 0 O 1 0 0 UCB3STE X 3 0 1 N A 0 1 0 DVSS 1 N A 0 1 1 DVSS 1 P10 1 UCB3CLK 2 1 P10 1 I O I 0 O 1 0 0 UCB3CLK X 3 0 1 N A 0 1 0 DVSS 1 N A 0 1 1 DVSS 1 P10 2 UCB3S...

Page 146: ...LAS826F MARCH 2015 REVISED MARCH 2017 www ti com Submit Documentation Feedback Product Folder Links MSP432P401R MSP432P401M Detailed Description Copyright 2015 2017 Texas Instruments Incorporated 6 12 6 Port P2 P2 4 to P2 7 Input Output With Schmitt Trigger Figure 6 8 shows the port diagram Table 6 67 summarizes the selection of the pin functions Functional representation only Figure 6 8 Py x Mod1...

Page 147: ... PIN NAME P2 x x FUNCTION CONTROL BITS OR SIGNALS 1 P2DIR x P2SEL1 x P2SEL0 x P2MAPx P2 4 PM_TA0 1 2 4 P2 4 I O I 0 O 1 0 0 X TA0 CCI1A 0 0 1 default TA0 1 1 N A 0 1 0 X DVSS 1 N A 0 1 1 X DVSS 1 P2 5 PM_TA0 2 2 5 P2 5 I O I 0 O 1 0 0 X TA0 CCI2A 0 0 1 default TA0 2 1 N A 0 1 0 X DVSS 1 N A 0 1 1 X DVSS 1 P2 6 PM_TA0 3 2 6 P2 6 I O I 0 O 1 0 0 X TA0 CCI3A 0 0 1 default TA0 3 1 N A 0 1 0 X DVSS 1 N...

Page 148: ...ions Table 6 68 Port P7 P7 0 to P7 3 Pin Functions PIN NAME P7 x x FUNCTION CONTROL BITS OR SIGNALS 1 P7DIR x P7SEL1 x P7SEL0 x P7MAPx P7 0 PM_SMCLK PM_DMAE0 0 P7 0 I O I 0 O 1 0 0 X DMAE0 0 0 1 default SMCLK 1 N A 0 1 0 X DVSS 1 N A 0 1 1 X DVSS 1 P7 1 PM_C0OUT PM_TA0CLK 1 P7 1 I O I 0 O 1 0 0 X TA0CLK 0 0 1 default C0OUT 1 N A 0 1 0 X DVSS 1 N A 0 1 1 X DVSS 1 P7 2 PM_C1OUT PM_TA1CLK 2 P7 2 I O ...

Page 149: ...ges 6 12 8 Port P9 P9 2 and P9 3 Input Output With Schmitt Trigger Figure 6 8 shows the port diagram Table 6 69 summarizes the selection of the pin functions Table 6 69 Port P9 P9 2 and P9 3 Pin Functions PIN NAME P9 x x FUNCTION CONTROL BITS OR SIGNALS P9DIR x P9SEL1 x P9SEL0 x P9 2 TA3 3 1 2 P9 2 I O I 0 O 1 0 0 TA3 CCI3A 0 0 1 TA3 3 1 N A 0 1 0 DVSS 1 N A 0 1 1 DVSS 1 P9 3 TA3 4 1 3 P9 3 I O I ...

Page 150: ...on is not available See the pin function tables 150 MSP432P401R MSP432P401M SLAS826F MARCH 2015 REVISED MARCH 2017 www ti com Submit Documentation Feedback Product Folder Links MSP432P401R MSP432P401M Detailed Description Copyright 2015 2017 Texas Instruments Incorporated 6 12 9 Port P4 P4 0 to P4 7 Input Output With Schmitt Trigger Figure 6 9 shows the port diagram Table 6 70 summarizes the selec...

Page 151: ...ctions PIN NAME P4 x x FUNCTION CONTROL BITS OR SIGNALS 1 P4DIR x P4SEL1 x P4SEL0 x P4 0 A13 2 0 P4 0 I O I 0 O 1 0 0 N A 0 0 1 DVSS 1 N A 0 1 0 DVSS 1 A13 3 X 1 1 P4 1 A12 2 1 P4 1 I O I 0 O 1 0 0 N A 0 0 1 DVSS 1 N A 0 1 0 DVSS 1 A12 3 X 1 1 P4 2 ACLK TA2CLK A11 2 P4 2 I O I 0 O 1 0 0 N A 0 0 1 ACLK 1 TA2CLK 0 1 0 DVSS 1 A11 3 X 1 1 P4 3 MCLK RTCCLK A10 3 P4 3 I O I 0 O 1 0 0 N A 0 0 1 MCLK 1 N ...

Page 152: ...Folder Links MSP432P401R MSP432P401M Detailed Description Copyright 2015 2017 Texas Instruments Incorporated Table 6 70 Port P4 P4 0 to P4 7 Pin Functions continued PIN NAME P4 x x FUNCTION CONTROL BITS OR SIGNALS 1 P4DIR x P4SEL1 x P4SEL0 x P4 7 A6 7 P4 7 I O I 0 O 1 0 0 N A 0 0 1 DVSS 1 N A 0 1 0 DVSS 1 A6 3 X 1 1 ...

Page 153: ...e 6 9 shows the port diagram Table 6 71 summarizes the selection of the pin functions Table 6 71 Port P5 P5 0 to P5 5 Pin Functions PIN NAME P5 x x FUNCTION CONTROL BITS OR SIGNALS 1 P5DIR x P5SEL1 x P5SEL0 x P5 0 A5 0 P5 0 I O I 0 O 1 0 0 N A 0 0 1 DVSS 1 N A 0 1 0 DVSS 1 A5 2 X 1 1 P5 1 A4 1 P5 1 I O I 0 O 1 0 0 N A 0 0 1 DVSS 1 N A 0 1 0 DVSS 1 A4 2 X 1 1 P5 2 A3 2 P5 2 I O I 0 O 1 0 0 N A 0 0 ...

Page 154: ...iver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals 6 12 11 Port P6 P6 0 and P6 1 Input Output With Schmitt Trigger Figure 6 9 shows the port diagram Table 6 72 summarizes the selection of the pin functions Table 6 72 Port P6 P6 0 and P6 1 Pin Functions PIN NAME P6 x x FUNCTION CONTROL BITS OR SIGNALS 1 P6DIR x P6SEL1 x P6SEL0 x P6 0 A15 2 0 P6 0 I O...

Page 155: ...6 9 shows the port diagram Table 6 73 summarizes the selection of the pin functions Table 6 73 Port P8 P8 2 to P8 7 Pin Functions PIN NAME P8 x x FUNCTION CONTROL BITS OR SIGNALS 1 P8DIR x P8SEL1 x P8SEL0 x P8 2 TA3 2 A23 2 2 P8 2 I O I 0 O 1 0 0 TA3 CCI2A 0 0 1 TA3 2 1 N A 0 1 0 DVSS 1 A23 3 X 1 1 P8 3 TA3CLK A22 2 3 P8 3 I O I 0 O 1 0 0 TA3CLK 0 0 1 DVSS 1 N A 0 1 0 DVSS 1 A22 3 X 1 1 P8 4 A21 2...

Page 156: ...river and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals 6 12 13 Port P9 P9 0 and P9 1 Input Output With Schmitt Trigger Figure 6 9 shows the port diagram Table 6 74 summarizes the selection of the pin functions Table 6 74 Port P9 P9 0 and P9 1 Pin Functions PIN NAME P9 x x FUNCTION CONTROL BITS OR SIGNALS 1 P9DIR x P9SEL1 x P9SEL0 x P9 0 A17 2 0 P9 0 I ...

Page 157: ...57 MSP432P401R MSP432P401M www ti com SLAS826F MARCH 2015 REVISED MARCH 2017 Submit Documentation Feedback Product Folder Links MSP432P401R MSP432P401M Detailed Description Copyright 2015 2017 Texas Instruments Incorporated 6 12 14 Port P5 P5 6 and P5 7 Input Output With Schmitt Trigger Figure 6 10 shows the port diagram Table 6 75 summarizes the selection of the pin functions Functional represent...

Page 158: ...nd the input Schmitt trigger to prevent parasitic cross currents when applying analog signals Selecting the C1 q input pin to the comparator multiplexer with the CEIPSEL or CEIMSEL bits automatically disables the output driver and input buffer for that pin regardless of the state of the associated CEPD q bit Table 6 75 Port P5 P5 6 and P5 7 Pin Functions PIN NAME P5 x x FUNCTION CONTROL BITS OR SI...

Page 159: ...59 MSP432P401R MSP432P401M www ti com SLAS826F MARCH 2015 REVISED MARCH 2017 Submit Documentation Feedback Product Folder Links MSP432P401R MSP432P401M Detailed Description Copyright 2015 2017 Texas Instruments Incorporated 6 12 15 Port P6 P6 2 to P6 5 Input Output With Schmitt Trigger Figure 6 11 shows the port diagram Table 6 76 summarizes the selection of the pin functions Functional representa...

Page 160: ...arasitic cross currents when applying analog signals Selecting the C1 q input pin to the comparator multiplexer with the CEIPSEL or CEIMSEL bits automatically disables the output driver and input buffer for that pin regardless of the state of the associated CEPD q bit Table 6 76 Port P6 P6 2 to P6 5 Pin Functions PIN NAME P6 x x FUNCTION CONTROL BITS OR SIGNALS 1 P6DIR x P6SEL1 x P6SEL0 x P6 2 UCB...

Page 161: ...161 MSP432P401R MSP432P401M www ti com SLAS826F MARCH 2015 REVISED MARCH 2017 Submit Documentation Feedback Product Folder Links MSP432P401R MSP432P401M Detailed Description Copyright 2015 2017 Texas Instruments Incorporated 6 12 16 Port P6 P6 6 and P6 7 Input Output With Schmitt Trigger Figure 6 12 shows the port diagram Table 6 77 summarizes the selection of the pin functions Functional represen...

Page 162: ...e output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals Selecting the C1 q input pin to the comparator multiplexer with the CEIPSEL or CEIMSEL bits automatically disables the output driver and input buffer for that pin regardless of the state of the associated CEPD q bit Table 6 77 Port P6 P6 6 and P6 7 Pin Functions PIN NAME P6 x x FUNCTION C...

Page 163: ...163 MSP432P401R MSP432P401M www ti com SLAS826F MARCH 2015 REVISED MARCH 2017 Submit Documentation Feedback Product Folder Links MSP432P401R MSP432P401M Detailed Description Copyright 2015 2017 Texas Instruments Incorporated 6 12 17 Port P8 P8 0 and P8 1 Input Output With Schmitt Trigger Figure 6 13 shows the port diagram Table 6 78 summarizes the selection of the pin functions Functional represen...

Page 164: ...parator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals Selecting the C0 q input pin to the comparator multiplexer with the CEIPSEL or CEIMSEL bits automatically disables the output driver and input buffer for that pin regardless of the state of the associated CEPD q bit Table 6 78 Port P8 P8 0 and P8 1 Pin Functions PIN NAM...

Page 165: ...2P401R MSP432P401M www ti com SLAS826F MARCH 2015 REVISED MARCH 2017 Submit Documentation Feedback Product Folder Links MSP432P401R MSP432P401M Detailed Description Copyright 2015 2017 Texas Instruments Incorporated 6 12 18 Port P10 P10 4 and P10 5 Input Output With Schmitt Trigger Figure 6 14 shows the port diagram Table 6 79 summarizes the selection of the pin functions Functional representation...

Page 166: ...mparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying analog signals Selecting the C0 q input pin to the comparator multiplexer with the CEIPSEL or CEIMSEL bits automatically disables the output driver and input buffer for that pin regardless of the state of the associated CEPD q bit Table 6 79 Port P10 P10 4 and P10 5 Pin Functions PIN...

Page 167: ...432P401R MSP432P401M www ti com SLAS826F MARCH 2015 REVISED MARCH 2017 Submit Documentation Feedback Product Folder Links MSP432P401R MSP432P401M Detailed Description Copyright 2015 2017 Texas Instruments Incorporated 6 12 19 Port P7 P7 4 to P7 7 Input Output With Schmitt Trigger Figure 6 15 shows the port diagram Table 6 80 summarizes the selection of the pin functions Functional representation o...

Page 168: ... Selecting the C0 q input pin to the comparator multiplexer with the CEIPSEL or CEIMSEL bits automatically disables the output driver and input buffer for that pin regardless of the state of the associated CEPD q bit Table 6 80 Port P7 P7 4 to P7 7 Pin Functions PIN NAME P7 x x FUNCTION CONTROL BITS OR SIGNALS 1 P7DIR x P7SEL1 x P7SEL0 x P7MAPx P7 4 PM_TA1 4 C0 5 2 4 P7 4 I O I 0 O 1 0 0 X TA1 CCI...

Page 169: ...ww ti com SLAS826F MARCH 2015 REVISED MARCH 2017 Submit Documentation Feedback Product Folder Links MSP432P401R MSP432P401M Detailed Description Copyright 2015 2017 Texas Instruments Incorporated 6 12 20 Port PJ PJ 0 and PJ 1 Input Output With Schmitt Trigger Figure 6 16 and Figure 6 17 show the port diagram Table 6 81 summarizes the selection of the pin functions Functional representation only Fi...

Page 170: ...1 0 1 1 PJSEL1 1 0 1 0 0 1 0 1 1 DVSS DVSS PJSEL0 0 LFXTBYPASS PJSEL1 0 170 MSP432P401R MSP432P401M SLAS826F MARCH 2015 REVISED MARCH 2017 www ti com Submit Documentation Feedback Product Folder Links MSP432P401R MSP432P401M Detailed Description Copyright 2015 2017 Texas Instruments Incorporated Functional representation only Figure 6 17 Port PJ PJ 1 Diagram ...

Page 171: ...general purpose I O 3 When PJ 0 is configured in bypass mode PJ 1 is configured as general purpose I O 4 With PJSEL0 1 1 or PJSEL1 1 1 the general purpose I O functionality is disabled No input function is available When configured as output the pin is actively pulled to zero Table 6 81 Port PJ PJ 0 and PJ 1 Pin Functions PIN NAME PJ x x FUNCTION CONTROL BITS OR SIGNALS 1 PJDIR x PJSEL1 1 PJSEL0 1...

Page 172: ...AS826F MARCH 2015 REVISED MARCH 2017 www ti com Submit Documentation Feedback Product Folder Links MSP432P401R MSP432P401M Detailed Description Copyright 2015 2017 Texas Instruments Incorporated 6 12 21 Port PJ PJ 2 and PJ 3 Input Output With Schmitt Trigger Figure 6 18 and Figure 6 19 show the port diagrams Table 6 82 summarizes the selection of the pin functions Functional representation only Fi...

Page 173: ...1 0 1 1 PJSEL1 2 0 1 0 0 1 0 1 1 DVSS DVSS PJSEL0 3 HFXTBYPASS PJSEL1 3 173 MSP432P401R MSP432P401M www ti com SLAS826F MARCH 2015 REVISED MARCH 2017 Submit Documentation Feedback Product Folder Links MSP432P401R MSP432P401M Detailed Description Copyright 2015 2017 Texas Instruments Incorporated Functional representation only Figure 6 19 Port PJ PJ 3 Diagram ...

Page 174: ...general purpose I O 3 When PJ 3 is configured in bypass mode PJ 2 is configured as general purpose I O 4 With PJSEL0 2 1 or PJSEL1 2 1 the general purpose I O functionality is disabled No input function is available When configured as output the pin is actively pulled to zero Table 6 82 Port PJ PJ 2 and PJ 3 Pin Functions PIN NAME PJ x x FUNCTION CONTROL BITS OR SIGNALS 1 PJDIR x PJSEL1 2 PJSEL0 2...

Page 175: ...3 summarizes the selection of the pin functions Table 6 83 Port PJ PJ 4 to PJ 5 Pin Functions PIN NAME PJ x x FUNCTION CONTROL BITS OR SIGNALS 1 SWJ MODE OF OPERATION 1 PJDIR x PJSEL1 x PJSEL0 x PJ 4 TDI 2 4 PJ 4 I O I 0 O 1 0 0 X TDI X 0 1 JTAG 4 wire DVcc SWD 2 wire DVcc X 1 X X PJ 5 TDO SWO 3 5 PJ 5 I O I 0 O 1 0 0 X TDO X 0 1 JTAG 4 wire SWO SWD 2 wire Hi Z X 1 X X 1 This pin is internally pul...

Page 176: ...cord Die Record Tag 0020101Ch 0000000Ch Die Record Length 00201020h 00000008h Die X Position 00201024h per unit Die Y Position 00201028h per unit Wafer ID 0020102Ch per unit Lot ID 00201030h per unit Reserved 00201034h per unit Reserved 00201038h per unit Reserved 0020103Ch per unit Test Results 00201040h per unit Clock System Calibration Clock System Calibration Tag 00201044h 00000003h Clock Syst...

Page 177: ...t ADC 1 2 V Reference Temperature Sensor 85 C 002010E0h per unit ADC 1 45 V Reference Temperature Sensor 30 C 002010E4h per unit ADC 1 45 V Reference Temperature Sensor 85 C 002010E8h per unit ADC 2 5 V Reference Temperature Sensor 30 C 002010ECh per unit ADC 2 5 V Reference Temperature Sensor 85 C 002010F0h per unit REF Calibration REF Calibration Tag 002010F4h 00000008h REF Calibration Length 00...

Page 178: ...iptor structure see Section 6 13 6 14 3 ARM Cortex M4F ROM Table Based Part Number The MSP432P4xx family of MCUs incorporates a part number for the device for the IDEs to recognize the device in addition to the device IDs specified in the device descriptors TLV This section describes how this information is organized on the device IEEE 1149 1 defines the use of a IDCODE register in the JTAG chain ...

Page 179: ...served for this purpose Part number PID1 and PID0 registers For the MSP432P4xx MCUs the Revision and RevAnd fields are used for tracking the major and minor revisions Also the Customer modified 4 bit field is used for extending the Part number to 16 bits to accommodate all of the fields needed by IEEE 1149 1 in the ROM table As an example the ROM table with IEEE 1149 1 complaint device IDCODE for ...

Page 180: ...debugging and optimum analog performance 7 1 1 Power Supply Decoupling and Bulk Capacitors TI recommends connecting a combination of a 4 7 µF plus a 100 nF low ESR ceramic decoupling capacitor to each AVCC and DVCC pin see Figure 7 1 Higher value capacitors may be used but can impact supply rail ramp up time Decoupling capacitors must be placed as close as possible to the pins that they decouple w...

Page 181: ... signal applications Proper ESD level protection should be considered to protect the device from unintended high voltage electrostatic discharge See MSP430 System Level ESD Considerations for guidelines 7 1 4 Do s and Don ts TI recommends powering AVCC and DVCC pins from the same source At a minimum during power up power down and device operation the voltage difference between AVCC and DVCC must n...

Page 182: ...citor values that are selected in the general guidelines filter out the high and low frequency ripple before the reference voltage enters the device In this case the 5 µF capacitor is used to buffer the reference pin and filter any low frequency ripple A 50 nF bypass capacitor is used to filter out any high frequency noise 7 2 1 3 Layout Guidelines Components that are shown in the partial schemati...

Page 183: ... necessarily representative of the final device s electrical specifications PMS Final silicon die that conforms to the device s electrical specifications but has not completed quality and reliability verification MSP Fully qualified production device Support tool development evolutionary flow MSPX Development support product that has not yet completed Texas Instruments internal qualification testi...

Page 184: ...8 1 Device Nomenclature 8 3 Tools and Software All MSP432 microcontrollers are supported by a wide variety of software and hardware development tools Tools are available from TI and various third parties See them all at TI 32 bit MSP432 microcontrollers Table 8 1 lists the supported debug features See the Code Composer Studio IDE 7 1 for SimpleLink MSP432 Microcontrollers User s Guide for details ...

Page 185: ...DE that supports all MSP microcontroller devices Code Composer Studio comprises a suite of embedded software utilities used to develop and debug embedded applications It includes an optimizing C C compiler source code editor project build environment debugger profiler and many other features For more information see the Code Composer Studio IDE 7 1 for SimpleLink MSP432 Microcontrollers User s Gui...

Page 186: ... exceptions to the functional specifications for each silicon revision of this device MSP432P401M Device Erratasheet Describes the known exceptions to the functional specifications for each silicon revision of this device User s Guides MSP432P4xx SimpleLink Microcontrollers Technical Reference Manual Detailed description of all modules and peripherals available in this device family Code Composer ...

Page 187: ...of these embedded applications can be diverse based the needs of the application Some applications might require operating at higher frequencies in the order of several megahertz while some other applications might require operating at lower frequencies in the order of a few tens or a few hundreds of kilohertz There are several microcontrollers in the market that offer good active mode power consu...

Page 188: ... be damaged by ESD Texas Instruments recommends that all integrated circuits be handled with appropriate precautions Failure to observe proper handling and installation procedures can cause damage ESD damage can range from subtle performance degradation to complete device failure Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the d...

Page 189: ...QUAD FLATPACK 4040149 B 11 96 50 26 0 13 NOM Gage Plane 0 25 0 45 0 75 0 05 MIN 0 27 51 25 75 1 12 00 TYP 0 17 76 100 SQ SQ 15 80 16 20 13 80 1 35 1 45 1 60 MAX 14 20 0 7 Seating Plane 0 08 0 50 M 0 08 NOTES A All linear dimensions are in millimeters B This drawing is subject to change without notice C Falls within JEDEC MS 026 ...

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Page 191: ...ID ARRAY NOTES 1 All linear dimensions are in millimeters Any dimensions in parenthesis is for reference only Dimensioning and tolerancing per ASME Y14 5M 2 This drawing is subject to change without notice 3 This is a Pb free solder ball design BALL A1 CORNER INDEX AREA SEATING PLANE BALL TYP 0 08 C J H G F E D C B A 1 2 3 0 15 C B A 0 05 C SYMM SYMM 4 5 6 7 8 9 SCALE 3 000 ...

Page 192: ...max height ZXH0080A BALL GRID ARRAY NOTES continued 3 Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints See Texas Instruments Literature No SBVA017 www ti com lit sbva017 SYMM SYMM LAND PATTERN EXAMPLE SCALE 15X C 1 2 3 A B D E F G H J 4 5 6 7 8 9 NON SOLDER MASK DEFINED PREFERRED SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK DEFINED ...

Page 193: ...1325 A 01 2014 NFBGA 1 mm max height ZXH0080A BALL GRID ARRAY NOTES continued 4 Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0 1 mm THICK STENCIL SCALE 20X C 1 2 3 A B D E F G H J 4 5 6 7 8 9 ...

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Page 196: ...U Level 3 260C 168 HR 40 to 85 MSP432P401R MSP432P401RIRGCR ACTIVE VQFN RGC 64 2000 Green RoHS no Sb Br CU NIPDAU Level 3 260C 168 HR 40 to 85 MSP432P401R MSP432P401RIRGCT ACTIVE VQFN RGC 64 250 Green RoHS no Sb Br CU NIPDAU Level 3 260C 168 HR 40 to 85 MSP432P401R MSP432P401RIZXHR ACTIVE NFBGA ZXH 80 2500 Green RoHS no Sb Br SNAGCU Level 3 260C 168 HR 40 to 85 MSP432 P401R MSP432P401RIZXHT ACTIVE...

Page 197: ... be inside parentheses Only one Device Marking contained in parentheses and separated by a will appear on a device If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device 6 Lead Ball Finish Orderable Devices may have multiple material finish options Finish options are separated by a vertical ruled line Lead Ball ...

Page 198: ...oduct s identified in such TI Resource NO OTHER LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN including but not limited to any patent right copyright mask work right or other intellectual property right relating to any combination machine or p...

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