From Module
Direction
0: Input
1: Output
To Module
PxOUT.y
DVSS
DVCC
1
TAx.y
TAxCLK
1
0
PxIN.y
EN
D
PxSEL.y
PxREN.y
1
0
PxSEL2.y
1
0
PxSEL.y
1
3
2
1
0
PxSEL2.y
PxIRQ.y
PxIE.y
EN
Set
Q
Interrupt
Edge
Select
PxSEL.y
PxIES.y
PxIFG.y
PxDIR.y
1
0
PxSEL.y
0
P1.0/TA0CLK/ADCCLK
P1.1/TA0.0
P1.2/TA0.1
P1.3/TA0.2
MSP430G2955
MSP430G2855
MSP430G2755
www.ti.com
SLAS800 – MARCH 2013
PORT SCHEMATICS
Port P1 Pin Schematic: P1.0 to P1.3, Input/Output With Schmitt Trigger
Copyright © 2013, Texas Instruments Incorporated
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