Texas Instruments MSP430G2755, Manual

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MSP430G2955
MSP430G2855
MSP430G2755
SLAS800 – MARCH 2013 www.ti.com
Table 2. Terminal Functions
TERMINAL
NO. I/O DESCRIPTION
NAME
DA RHA
P1.0/ General-purpose digital I/O pin
TACLK/ 31 29 I/O Timer_A, clock signal TACLK input
ADC10CLK ADC10, conversion clock
P1.1/ General-purpose digital I/O pin
32 30 I/O
TA0.0 Timer_A, capture: CCI0A input, compare: OUT0 output or BSL transmit
P1.2/ General-purpose digital I/O pin
33 31 I/O
TA0.1 Timer_A, capture: CCI1A input, compare: OUT1 output
P1.3/ General-purpose digital I/O pin
34 32 I/O
TA0.2 Timer_A, capture: CCI2A input, compare: OUT2 output
P1.4/ General-purpose digital I/O pin
SMCLK/ 35 33 I/O SMCLK signal output
TCK JTAG test clock, input terminal for device programming and test
P1.5/ General-purpose digital I/O pin
TA0.0/ 36 34 I/O Timer_A, compare: OUT0 output
TMS JTAG test mode select, input terminal for device programming and test
P1.6/ General-purpose digital I/O pin /
TA0.1/ Timer_A, compare: OUT1 output
37 35 I/O
TDI/ JTAG test data input terminal during programming and test
TCLK JTAG test clock input terminal during programming and test
P1.7/ General-purpose digital I/O pin
TA0.2/ Timer_A, compare: OUT2 output
38 36 I/O
TDO/ JTAG test data output terminal during programming and test
TDI
(1)
JTAG test data input terminal during programming and test
P2.0/ General-purpose digital I/O pin
TA1CLK/ Timer1_A3.TACLK
8 6 I/O
ACLK/ ACLK output
A0 ADC10, analog input A0
P2.1/ General-purpose digital I/O pin
TAINCLK/ Timer_A, clock signal at INCLK
9 7 I/O
SMCLK/ SMCLK signal output
A1 ADC10, analog input A1
P2.2/ General-purpose digital I/O pin
TA0.0/ 10 8 I/O Timer_A, capture: CCI0B input or BSL receive, compare: OUT0 output
A2 ADC10, analog input A2
P2.3/ General-purpose digital I/O pin
TA0.1/ Timer_A, capture CCI1B input, compare: OUT1 output
A3/ 29 27 I/O ADC10, analog input A3
VREF-/ Negative reference voltage output
VEREF- Negative reference voltage input
P2.4/ General-purpose digital I/O pin
TA0.2/ Timer_A, compare: OUT2 output
A4/ 30 28 I/O ADC10, analog input A4
VREF+/ Positive reference voltage output
VEREF+ Positive reference voltage input
(1) TDO or TDI is selected via JTAG instruction.
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