P3.0/UCB0STE/UCA0CLK/A5
0
From Module
To Module
From Module
PxOUT.y
DVSS
DVCC
1
TAx.y
TAxCLK
Bus
Keeper
EN
1
0
PxIN.y
EN
D
PxSEL.y
PxREN.y
1
0
PxSEL2.y
1
0
INCHx = y
To ADC10
PxSEL.y
1
3
2
1
0
PxSEL2.y
PxIRQ.y
PxIE.y
EN
Set
Q
Interrupt
Edge
Select
PxSEL.y
PxIES.y
PxIFG.y
Direction
0: Input
1: Output
PxDIR.y
From Module
PxSEL.y
3
2
1
0
PxSEL2.y
ADC10AE0.y
MSP430G2955
MSP430G2855
MSP430G2755
SLAS800 – MARCH 2013
www.ti.com
Port P3 Pin Schematic: P3.0 to P3.7, Input/Output With Schmitt Trigger
56
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