MSP430G2955
MSP430G2855
MSP430G2755
SLAS800 – MARCH 2013
www.ti.com
Special Function Registers (SFRs)
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
Legend
rw:
Bit can be read and written.
rw-0,1:
Bit can be read and written. It is reset or set by PUC.
rw-(0,1):
Bit can be read and written. It is reset or set by POR.
SFR bit is not present in device.
Table 6. Interrupt Enable Register 1 and 2
Address
7
6
5
4
3
2
1
0
00h
ACCVIE
NMIIE
OFIE
WDTIE
rw-0
rw-0
rw-0
rw-0
WDTIE
Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog timer is configured in
interval timer mode.
OFIE
Oscillator fault interrupt enable
NMIIE
(Non)maskable interrupt enable
ACCVIE
Flash access violation interrupt enable
Address
7
6
5
4
3
2
1
0
01h
UCB0TXIE
UCB0RXIE
UCA0TXIE
UCA0RXIE
rw-0
rw-0
rw-0
rw-0
UCA0RXIE
USCI_A0 receive interrupt enable
UCA0TXIE
USCI_A0 transmit interrupt enable
UCB0RXIE
USCI_B0 receive interrupt enable
UCB0TXIE
USCI_B0 transmit interrupt enable
Table 7. Interrupt Flag Register 1 and 2
Address
7
6
5
4
3
2
1
0
02h
NMIIFG
RSTIFG
PORIFG
OFIFG
WDTIFG
rw-0
rw-(0)
rw-(1)
rw-1
rw-(0)
WDTIFG
Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on V
CC
power-on or a reset condition at the RST/NMI pin in reset mode.
OFIFG
Flag set on oscillator fault.
PORIFG
Power-on reset interrupt flag. Set on V
CC
power-up.
RSTIFG
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on V
CC
power-up.
NMIIFG
Set via RST/NMI pin
Address
7
6
5
4
3
2
1
0
03h
UCB0TXIFG
UCB0RXIFG
UCA0TXIFG
UCA0RXIFG
rw-1
rw-0
rw-1
rw-0
UCA0RXIFG
USCI_A0 receive interrupt flag
UCA0TXIFG
USCI_A0 transmit interrupt flag
UCB0RXIFG
USCI_B0 receive interrupt flag
UCB0TXIFG
USCI_B0 transmit interrupt flag
10
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