MSP430G2955
MSP430G2855
MSP430G2755
SLAS800 – MARCH 2013
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Timer_A3 (TA0, TA1)
Timer0_A3 and Timer1_A3 are 16-bit timers/counters with three capture/compare registers. Timer_A3 can
support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 12. Timer0_A3 Signal Connections
INPUT PIN NUMBER
MODULE
OUTPUT PIN NUMBER
DEVICE INPUT
MODULE
MODULE
OUTPUT
SIGNAL
INPUT NAME
BLOCK
DA38
RHA40
DA38
RHA40
SIGNAL
P1.0 - 31
P1.0-29
TACLK
TACLK
ACLK
ACLK
Timer
NA
SMCLK
SMCLK
P2.1 - 9
P2.1 - 7
TACLK
INCLK
P1.1 - 32
P1.1 - 30
TA0.0
CCI0A
P1.1- 32
P1.1 - 30
P2.2 - 10
P2.2 - 8
ACLK
CCI0B
P2.2 - 10
P2.2 - 8
CCR0
TA0
V
SS
GND
P1.5 - 36
P1.5 - 34
V
CC
V
CC
P1.2 - 33
P1.2 - 31
TA0.1
CCI1A
P1.2 - 33
P1.2 - 31
P2.3 - 29
P2.3 - 27
TA0.1
CCI1B
P2.3 - 29
P2.3 - 27
CCR1
TA1
V
SS
GND
P1.6 - 37
P1.6 - 35
V
CC
V
CC
P1.3 - 34
P1.3 - 32
TA0.2
CCI2A
P1.3 - 34
P1.3 - 32
ACLK (internal)
CCI2B
P2.4 - 30
P2.4 - 28
CCR2
TA2
V
SS
GND
P1.7 - 38
P1.7 - 36
V
CC
V
CC
Table 13. Timer1_A3 Signal Connections
INPUT PIN NUMBER
MODULE
OUTPUT PIN NUMBER
DEVICE INPUT
MODULE
MODULE
OUTPUT
SIGNAL
INPUT NAME
BLOCK
DA38
RHA40
DA38
RHA40
SIGNAL
P2.0 - 8
P2.0 - 6
TACLK
TACLK
ACLK
ACLK
Timer
NA
SMCLK
SMCLK
PinOsc
PinOsc
TACLK
INCLK
P2.5 - 3
P2.5 - 40
TA1.0
CCI0A
P2.5 - 3
P2.5 - 40
TA1.0
CCI0B
CCR0
TA0
V
SS
GND
V
CC
V
CC
P3.6 - 27
P3.6 - 25
TA1.1
CCI1A
P3.6 - 27
P3.6 - 25
CAOUT
CCI1B
CCR1
TA1
V
SS
GND
V
CC
V
CC
P3.7 - 28
P3.7 - 26
TA1.2
CCI2A
P3.7 - 28
P3.7 - 26
PinOsc
PinOsc
TA1.2
CCI2B
CCR2
TA2
V
SS
GND
V
CC
V
CC
14
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