P2.4/TA0.2/A4/VREF+/VEREF+
Direction
0: Input
1: Output
To Module
From ADC10
PxOUT.y
DVSS
DVCC
1
TAx.y
TAxCLK
Bus
Keeper
EN
1
0
PxIN.y
EN
D
PxSEL.y
PxREN.y
1
0
PxDIR.y
1
0,2,3
PxSEL2.y
PxSEL.y
1
0
INCHx = y
To ADC10
To ADC10 VREF+
PxSEL.y
1
3
2
1
0
0
PxSEL2.y
PxIRQ.y
PxIE.y
EN
Set
Q
Interrupt
Edge
Select
PxSEL.y
PxIES.y
PxIFG.y
ADC10AE0.y
PxSEL2.y
MSP430G2955
MSP430G2855
MSP430G2755
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SLAS800 – MARCH 2013
Copyright © 2013, Texas Instruments Incorporated
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MSP430G2955 MSP430G2855 MSP430G2755
