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Texas Instruments MSP430G2755, Manual

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Texas Instruments MSP430G2755 Manual Download Page 3

Basic Clock

RAM

Brownout

Protection

RST/NMI

VCC

VSS

MCLK

SMCLK

Watchdog

WDT+

15 or 16 Bit

3 CC

Registers

16MHz

CPU

incl. 16

Registers

Emulation

(2BP)

XOUT

JTAG

Interface

Flash

56 kB
48 kB
32 kB

ACLK

XIN

MDB

MAB

Spy-Bi-Wire

3 CC

Registers,

Shadow

Register

USCI_A0:

UART, LIN,

IrDA,SPI

USCI_B0:

SPI,I2C

ADC

10-Bit

12

Channels,
Autoscan,

DTC

Ports P1, P2

2x8 I/O,

Interrupt

capability,

Pullup or
pulldown

resistors

P1.x, P2.x

2x8

P3.x, P4.x

2x8

4 kB

Timer0_A3

3 CC

Registers

Timer1_A3

Timer0_B3

8

Channels

Ports P3, P4

2x8 I/O,

Pullup or
pulldown

resistors

1

DVSS

P1.5/T

A0.0/TMS

P1.0/TA0CLK/ADC10CLK

P1.1/TA0.0

P1.2/T

A0.1

P1.3/T

A0.2

P1.4/SMCLK/TCK

13

P2.4/TA0.2/A4/VREF+/VEREF+

P2.5/T

A1.0/ROSC

DVCC

TEST/SBWTCK

P1.6/T

A0.1/TDI/TCLK

2

3

4

5

6

7

8

10

9

12

14 15 16 17 18 19

30

29

28

27

26

25

24

23

21

22

38

39

37 36 35 34 33 32

XOUT/P2.7

XIN/P2.6

DVSS

RST/NMI/SBWTDIO

P2.0/TA1CLK/ACLK/A0

P2.1/TA0INCLK/SMCLK/A1

P2.2/TA0.0/A2

P3.0/UCB0STE/UCA0CLK/A5

P3.1/UCB0SIMO/UCB0SDA

DVCC

P1.7/T

A0.2/TDO/TDI

P2.3/TA0.1/A3/VREF−/VEREF−

P3.7/TA1.2/A7

P3.6/TA1.1/A6

P3.5/UCA0RXD/UCA0SOMI

P3.4/UCA0TXD/UCA0SIMO

A

VCC

A

VSS

P3.2/UCB0SOMI/UCB0SCL

P3.3/UCB0CLK/UCA0STE

P4.0/TB0.0/CA0

P4.1/TB0.1/CA1

P4.2/TB0.2/CA2

P4.3/TB0.0/A12

/CA3

P4.4/TB0.1/A13

/CA4

P4.5/TB0.2/A14

/CA5

P4.6/TB0OUTH/A15/CA6

P4.7/TB0CLK/CA7

MSP430G2955
MSP430G2855
MSP430G2755

www.ti.com

SLAS800 – MARCH 2013

Device Pinout, 40-Pin QFN (RHA Package)

Functional Block Diagram

Copyright © 2013, Texas Instruments Incorporated

Submit Documentation Feedback

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Product Folder Links:

MSP430G2955 MSP430G2855 MSP430G2755

Summary of Contents for MSP430G2755

Page 1: ...d I O Pins For Complete Module Descriptions See the MSP430x2xx Family User s Guide SLAU144 DESCRIPTION The Texas Instruments MSP430 family of ultra low power microcontrollers consists of several devic...

Page 2: ...0G2955 MSP430G2855 MSP430G2755 SLAS800 MARCH 2013 www ti com Table 1 Available Options 1 2 Flash RAM Timer_A COMP_A ADC10 USCI_A0 Package Device BSL EEM Clock I O KB B Timer_B Channels Channels USCI_B...

Page 3: ...F P2 5 TA1 0 ROSC DVCC TEST SBWTCK P1 6 TA0 1 TDI TCLK 2 3 4 5 6 7 8 10 9 12 14 15 16 17 18 19 30 29 28 27 26 25 24 23 21 22 38 39 37 36 35 34 33 32 XOUT P2 7 XIN P2 6 DVSS RST NMI SBWTDIO P2 0 TA1CLK...

Page 4: ...test clock input terminal during programming and test P1 7 General purpose digital I O pin TA0 2 Timer_A compare OUT2 output 38 36 I O TDO JTAG test data output terminal during programming and test T...

Page 5: ...eral purpose digital I O pin UCA0TXD 25 23 I O USCI_A0 transmit data output in UART mode UCA0SIMO USCI_A0 slave in master out in SPI mode P3 5 General purpose digital I O pin UCA0RXD 26 24 I O USCI_A0...

Page 6: ...igh impedance CAOUT 23 21 I O Comparator_A Output A15 ADC10 analog input A15 CA6 Comparator_A CA6 input P4 7 General purpose digital I O pinCB0 TBCLK Timer_B clock signal TBCLK input 24 22 I O CAOUT C...

Page 7: ...pherals are connected to the CPU using data address and control buses and can be handled with all instructions The instruction set consists of the original 51 instructions with three formats and seven...

Page 8: ...SMCLK remain active MCLK is disabled Low power mode 1 LPM1 CPU is disabled ACLK and SMCLK remain active MCLK is disabled DCO s dc generator is disabled if DCO not used in active mode Low power mode 2...

Page 9: ...CI_B0 transmit UCA0TXIFG UCB0TXIFG 2 6 maskable 0FFECh 22 USCI_B0 I2C receive or transmit ADC10 ADC10IFG 4 maskable 0FFEAh 21 Reserved 0FFE8h 20 I O Port P2 up to eight flags P2IFG 0 to P2IFG 7 2 4 ma...

Page 10: ...01h UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE rw 0 rw 0 rw 0 rw 0 UCA0RXIE USCI_A0 receive interrupt enable UCA0TXIE USCI_A0 transmit interrupt enable UCB0RXIE USCI_B0 receive interrupt enable UCB0TXIE USC...

Page 11: ...SP430 memory via the BSL is protected by user defined password For complete description of the features of the BSL and its implementation see the MSP430 Programming Via the Bootstrap Loader User s Gui...

Page 12: ...n clock source and stabilizes in less than 1 s The basic clock module provides the following clock signals Auxiliary clock ACLK sourced either from a 32768 Hz watch crystal or the internal LF oscillat...

Page 13: ...x0007 byte CAL_DCO_8MHZ 0x0006 byte CAL_BC1_12MHZ 0x0005 byte CAL_DCO_12MHZ 0x0004 byte CAL_BC1_16MHZ 0x0003 byte CAL_DCO_16MHZ 0x0002 byte Brownout The brownout circuit is implemented to provide the...

Page 14: ...10 P2 2 8 CCR0 TA0 VSS GND P1 5 36 P1 5 34 VCC VCC P1 2 33 P1 2 31 TA0 1 CCI1A P1 2 33 P1 2 31 P2 3 29 P2 3 27 TA0 1 CCI1B P2 3 29 P2 3 27 CCR1 TA1 VSS GND P1 6 37 P1 6 35 VCC VCC P1 3 34 P1 3 32 TA0...

Page 15: ...LK internal CCI2B P4 5 22 P4 5 20 CCR2 TB2 VSS GND VCC VCC Universal Serial Communications Interface USCI The USCI module is used for serial data communication The USCI module supports synchronous com...

Page 16: ...Capture compare register TA0CCR1 0174h Capture compare register TA0CCR0 0172h Timer_A register TA0R 0170h Capture compare control TA0CCTL2 0166h Capture compare control TA0CCTL1 0164h Capture compare...

Page 17: ...USCI_A0 IrDA transmit control UCA0IRTCTL 05Eh USCI_A0 auto baud rate control UCA0ABCTL 05Dh ADC10 ADC analog enable 0 ADC10AE0 04Ah ADC analog enable 1 ADC10AE1 04Bh ADC data transfer control register...

Page 18: ...output P2OUT 029h Port P2 input P2IN 028h Port P1 Port P1 selection 2 P1SEL2 041h Port P1 resistor enable P1REN 027h Port P1 selection P1SEL 026h Port P1 interrupt enable P1IE 025h Port P1 interrupt e...

Page 19: ...use 3 Higher temperature may be applied during board soldering according to the current JEDEC J STD 020 specification with peak reflow temperatures not higher than classified on the device label on th...

Page 20: ...TYP MAX UNIT fDCO fMCLK fSMCLK 1 MHz 2 2 V 250 fACLK 0 Hz Program executes in flash Active mode AM IAM 1MHz BCSCTL1 CALBC1_1MHZ A current at 1 MHz 3 V 350 450 DCOCTL CALDCO_1MHZ CPUOFF 0 SCG0 0 SCG1...

Page 21: ...MCLK fSMCLK 0 MHz Low power mode 3 fACLK 32768 Hz ILPM3 LFXT1 25 C 2 2 V 1 0 1 5 A LPM3 current 4 CPUOFF 1 SCG0 1 SCG1 1 OSCOFF 0 fDCO fMCLK fSMCLK 0 MHz Low power mode 3 fACLK from internal LF oscill...

Page 22: ...y The port pin is selected for input and the pullup pulldown resistor is disabled Outputs Ports Px over recommended ranges of supply voltage and operating free air temperature unless otherwise noted P...

Page 23: ...3 5 VCC 3 V P1 7 TA 25 C TA 85 C OL I Typical Low Level Output Current mA MSP430G2955 MSP430G2855 MSP430G2755 www ti com SLAS800 MARCH 2013 Typical Characteristics Outputs over recommended ranges of s...

Page 24: ...illation frequency 3 V kHz P2 0 to P2 5 CL 20 pF RL 100 k 1 2 1000 foP2 6 7 Port output oscillation frequency P2 6 and P2 7 CL 20 pF RL 100 k 1 2 3 V 700 kHz P3 y CL 10 pF RL 100 k 1 2 1800 foP3 x Por...

Page 25: ...Pulse duration needed at RST NMI pin t reset 2 2 V 2 s to accepted reset internally 1 The current consumption of the brownout module is already included in the ICC current consumption data The voltage...

Page 26: ...p V tpw Pulse Width s VCC 3 V MSP430G2955 MSP430G2855 MSP430G2755 SLAS800 MARCH 2013 www ti com Typical Characteristics POR and BOR Figure 13 VCC drop Level With a Square Voltage Drop to Generate a PO...

Page 27: ...cy 7 3 RSELx 7 DCOx 3 MODx 0 3 V 0 80 1 50 MHz fDCO 8 3 DCO frequency 8 3 RSELx 8 DCOx 3 MODx 0 3 V 1 6 MHz fDCO 9 3 DCO frequency 9 3 RSELx 9 DCOx 3 MODx 0 3 V 2 3 MHz fDCO 10 3 DCO frequency 10 3 RS...

Page 28: ...MHZ 8 MHz tolerance overall DCOCTL CALDCO_8MHZ 40 C to 85 C 2 2 V to 3 6 V 6 3 6 calibrated at 30 C and 3 V BCSCTL1 CALBC1_12MHZ 12 MHz tolerance over DCOCTL CALDCO_12MHZ 0 C to 85 C 3 V 3 0 5 3 tempe...

Page 29: ...3 V 1 5 s or LPM4 1 DCOCTL CALDCO_1MHZ CPU wake up time from LPM3 or 1 fMCLK tCPU LPM3 4 LPM4 2 tClock LPM3 4 1 The DCO clock wake up time is measured from the edge of an external wake up signal for e...

Page 30: ...ended ranges of supply voltage and operating free air temperature unless otherwise noted PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT DCOR 1 fDCO ROSC DCO output frequency with ROSC RSELx 4 DCOx 3 M...

Page 31: ...e XIN and XOUT pins e Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins f If conformal coating is used ensure that it does not induce capacitive or resi...

Page 32: ...ice and the crystal as short as possible b Design a good ground plane around the oscillator pins c Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT d Avoid running PC...

Page 33: ...HF Mode XTS 1 OSCILLATION ALLOWANCE OSCILLATOR SUPPLY CURRENT vs vs CRYSTAL FREQUENCY CRYSTAL FREQUENCY CL eff 15 pF TA 25 C CL eff 15 pF TA 25 C Figure 20 Figure 21 Timer_A Timer_B over recommended...

Page 34: ...above 1 MHz 2 Pulses on the UART receive input UCxRX shorter than the UART receive deglitch time are suppressed To ensure that pulses are correctly recognized their duration should exceed the maximum...

Page 35: ...re 25 PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT tSTE LEAD STE lead time STE low to clock 3 V 50 ns tSTE LAG STE lag time Last clock to STE high 3 V 10 ns tSTE ACC STE access time STE low to SOMI...

Page 36: ...TYP MAX UNIT I DD See 1 CAON 1 CARSEL 0 CAREF 0 3 V 45 A CAON 1 CARSEL 0 I Refladder CAREF 1 2 or 3 3 V 45 A RefDiode No load at CA0 and CA1 V IC Common mode input voltage CAON 1 3 V 0 VCC 1 V PCA0 1...

Page 37: ...600 650 V 2 2 V CC Typical T Free Air Temperature C A V Reference Voltage mV RefVT 45 25 5 15 35 55 75 95 115 MSP430G2955 MSP430G2855 MSP430G2755 www ti com SLAS800 MARCH 2013 Typical Characteristics...

Page 38: ...urrent with ADC10SR 0 4 REF2_5V 0 REFOUT 1 ADC10SR 0 fADC10CLK 5 0 MHz Reference buffer supply ADC10ON 0 REFON 1 IREFB 1 25 C 3 V 0 5 mA current with ADC10SR 1 4 REF2_5V 0 REFOUT 1 ADC10SR 1 Only one...

Page 39: ...d regulation 3 V LSB IVREF 500 A 100 A Analog input voltage VAx 1 25 V 2 REF2_5V 1 IVREF 100 A 900 A VREF load regulation VAx 0 5 VREF 3 V 400 ns response time Error of conversion result 1 LSB ADC10SR...

Page 40: ...curacy limits the maximum negative external reference voltage Higher reference voltage levels may be applied with reduced accuracy requirements 5 The accuracy limits the minimum external differential...

Page 41: ...on 4 No additional current is needed The VMID is used during sampling 5 The on time tVMID on is included in the sampling time tVMID sample no additional on time is needed Flash Memory over recommended...

Page 42: ...urn to normal operation time 2 2 V 15 100 s fTCK TCK input frequency 2 2 2 V 0 5 MHz RInternal Internal pulldown resistance on TEST 2 2 V 25 60 90 k 1 Tools accessing the Spy Bi Wire interface need to...

Page 43: ...ge Select PxSEL y PxIES y PxIFG y PxDIR y 1 0 PxSEL y 0 P1 0 TA0CLK ADCCLK P1 1 TA0 0 P1 2 TA0 1 P1 3 TA0 2 MSP430G2955 MSP430G2855 MSP430G2755 www ti com SLAS800 MARCH 2013 PORT SCHEMATICS Port P1 Pi...

Page 44: ...0 1 P1 1 P1 x I O I 0 O 1 0 0 TA0 0 Timer0_A3 CCI0A 0 1 0 1 Timer0_A3 TA0 1 1 0 Pin Osc Capacitive sensing X 0 1 P1 2 P1 x I O I 0 O 1 0 0 TA0 1 Timer0_A3 CCI1A 0 1 0 2 Timer0_A3 TA1 1 1 0 Pin Osc Ca...

Page 45: ...y 1 3 2 1 0 PxSEL2 y From JTAG To JTAG PxIRQ y PxIE y EN Set Q Interrupt Edge Select PxSEL y PxIES y PxIFG y Direction 0 Input 1 Output PxDIR y From Module PxSEL y 3 2 1 0 PxSEL2 y 0 MSP430G2955 MSP4...

Page 46: ...I O I 0 O 1 0 0 0 TA0 0 Timer0_A3 TA0 1 1 0 0 5 TMS TMS X X X 1 Pin Osc Capacitive sensing X 0 1 0 P1 6 P1 x I O I 0 O 1 0 0 0 TA0 1 Timer0_A3 TA1 1 1 0 0 TDI 6 TDI X X X 1 TCLK TCLK X X X 1 Pin Osc...

Page 47: ...SEL y 1 0 INCHx y To ADC10 PxSEL y 1 3 2 1 0 0 PxSEL2 y PxIRQ y PxIE y EN Set Q Interrupt Edge Select PxSEL y PxIES y PxIFG y ADC10AE0 y PxSEL2 y MSP430G2955 MSP430G2855 MSP430G2755 www ti com SLAS800...

Page 48: ...y PxSEL y 1 0 INCHx y To ADC10 To ADC10 VREF 1 0 VSS SREF2 PxSEL y 1 3 2 1 0 0 PxSEL2 y PxIRQ y PxIE y EN Set Q Interrupt Edge Select PxSEL y PxIES y PxIFG y ADC10AE0 y PxSEL2 y MSP430G2955 MSP430G285...

Page 49: ...PxSEL2 y PxSEL y 1 0 INCHx y To ADC10 To ADC10 VREF PxSEL y 1 3 2 1 0 0 PxSEL2 y PxIRQ y PxIE y EN Set Q Interrupt Edge Select PxSEL y PxIES y PxIFG y ADC10AE0 y PxSEL2 y MSP430G2955 MSP430G2855 MSP43...

Page 50: ...1 0 2 3 PxSEL2 y PxSEL y 1 0 DCOR to from DCO PxSEL y 1 3 2 1 0 0 PxSEL2 y PxIRQ y PxIE y EN Set Q Interrupt Edge Select PxSEL y PxIES y PxIFG y PxSEL2 y MSP430G2955 MSP430G2855 MSP430G2755 SLAS800 MA...

Page 51: ...0 2 Timer0_A3 TA0 1 1 0 0 A2 A2 X X X 1 y 2 Pin Osc Capacitive sensing X 0 1 0 P2 3 P2 x I O I 0 O 1 0 0 0 TA0 1 Timer0_A3 CCI1B 0 1 0 0 Timer0_A3 TA1 1 1 0 0 A3 3 A3 X X X 1 y 3 VREF VREF X X X 1 VE...

Page 52: ...PxIE y EN Set Q Interrupt Edge Select PxSEL y PxIES y PxIFG y 1 0 XOUT P2 7 LF off LFXT1CLK PxSEL 6 and PxSEL 7 BCSCTL3 LFXT1Sx 11 MSP430G2955 MSP430G2855 MSP430G2755 SLAS800 MARCH 2013 www ti com Po...

Page 53: ...SIGNALS 1 PIN NAME P2 x x FUNCTION P2SEL 6 P2SEL2 6 P2DIR x P2SEL 7 P2SEL2 7 1 0 XIN XIN 0 1 0 0 0 P2 6 6 P2 x I O I 0 O 1 X 0 0 1 Pin Osc Capacitive sensing X X X 1 X don t care Copyright 2013 Texas...

Page 54: ...xIE y EN Set Q Interrupt Edge Select PxSEL y PxIES y PxIFG y 1 0 XIN LF off LFXT1CLK PxSEL 6 and PxSEL 7 BCSCTL3 LFXT1Sx 11 from P2 6 MSP430G2955 MSP430G2855 MSP430G2755 SLAS800 MARCH 2013 www ti com...

Page 55: ...IGNALS 1 PIN NAME P2 x x FUNCTION P2SEL 6 P2SEL2 6 P2DIR x P2SEL 7 P2SEL2 7 1 0 XOUT XOUT 1 1 0 0 0 P2 7 7 P2 x I O I 0 O 1 X 0 0 1 Pin Osc Capacitive sensing X X X 1 X don t care Copyright 2013 Texas...

Page 56: ...y EN Set Q Interrupt Edge Select PxSEL y PxIES y PxIFG y Direction 0 Input 1 Output PxDIR y From Module PxSEL y 3 2 1 0 PxSEL2 y ADC10AE0 y MSP430G2955 MSP430G2855 MSP430G2755 SLAS800 MARCH 2013 www...

Page 57: ...y PxREN y 1 0 PxSEL2 y 1 0 PxSEL y 1 3 2 1 0 PxSEL2 y PxIRQ y PxIE y EN Set Q Interrupt Edge Select PxSEL y PxIES y PxIFG y Direction 0 Input 1 Output PxDIR y From Module PxSEL y 3 2 1 0 PxSEL2 y MSP...

Page 58: ...1 0 2 3 PxSEL2 y PxSEL y 1 0 INCHx y To ADC10 PxSEL y 1 3 2 1 0 0 PxSEL2 y PxIRQ y PxIE y EN Set Q Interrupt Edge Select PxSEL y PxIES y PxIFG y ADC10AE0 y PxSEL2 y MSP430G2955 MSP430G2855 MSP430G275...

Page 59: ...3 P3 x I O I 0 O 1 0 0 n a UCB0CLK UCB0CLK from USCI 1 0 n a 3 UCA0STE UCA0STE from USCI 1 0 n a Pin Osc Capacitive sensing X 0 1 n a P3 4 P3 x I O I 0 O 1 0 0 n a UCA0TXD UCA0TXD from USCI 1 0 n a 4...

Page 60: ...Interrupt Edge Select PxSEL y PxIES y PxIFG y Direction 0 Input 1 Output PxDIR y From Module PxSEL y 3 2 1 0 PxSEL2 y From Comparator To Comparator CAPD y MSP430G2955 MSP430G2855 MSP430G2755 SLAS800...

Page 61: ...ADC10 PxSEL y 1 3 2 1 0 PxSEL2 y PxIRQ y PxIE y EN Set Q Interrupt Edge Select PxSEL y PxIES y PxIFG y Direction 0 Input 1 Output PxDIR y From Module PxSEL y 3 2 1 0 PxSEL2 y ADC10AE0 y From Comparat...

Page 62: ...PxIRQ y PxIE y EN Set Q Interrupt Edge Select PxSEL y PxIES y PxIFG y Direction 0 Input 1 Output PxDIR y From Module PxSEL y 3 2 1 0 PxSEL2 y From Comparator To Comparator CAPD y MSP430G2955 MSP430G28...

Page 63: ...Timer0_B3 CCI0A 0 1 0 0 0 Timer0_B3 TA0 1 1 0 0 0 3 A12 A12 X X X 1 y 12 0 CA3 CA3 X X X 0 1 y 3 Pin Osc Capacitive sensing X 0 1 0 0 P4 4 P4 x I O I 0 O 1 0 0 0 0 TB0 1 Timer0_B3 CCI1A 0 1 0 0 0 Time...

Page 64: ...85 G2955 MSP430G2955IDA38R ACTIVE TSSOP DA 38 2000 Green RoHS no Sb Br CU NIPDAU Level 2 260C 1 YEAR 40 to 85 G2955 MSP430G2955IRHA40R ACTIVE VQFN RHA 40 2500 Green RoHS no Sb Br CU NIPDAU Level 3 260...

Page 65: ...ay have multiple material finish options Finish options are separated by a vertical ruled line Lead Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width Import...

Page 66: ...40 250 180 0 16 4 6 3 6 3 1 1 12 0 16 0 Q2 MSP430G2855IDA38R TSSOP DA 38 2000 330 0 24 4 8 6 13 0 1 8 12 0 24 0 Q1 MSP430G2855IRHA40R VQFN RHA 40 2500 330 0 16 4 6 3 6 3 1 1 12 0 16 0 Q2 MSP430G2855IR...

Page 67: ...T VQFN RHA 40 250 210 0 185 0 35 0 MSP430G2855IDA38R TSSOP DA 38 2000 367 0 367 0 45 0 MSP430G2855IRHA40R VQFN RHA 40 2500 367 0 367 0 38 0 MSP430G2855IRHA40T VQFN RHA 40 250 210 0 185 0 35 0 MSP430G2...

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Page 73: ...duct s identified in such TI Resource NO OTHER LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY...

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