t
SU,MI
t
HD,MI
UCLK
SOMI
SIMO
t
VALID,MO
CKPL = 0
CKPL = 1
1/f
UCxCLK
t
HD,MO
t
LO/HI
t
LO/HI
t
SU,MI
t
HD,MI
UCLK
SOMI
SIMO
t
VALID,MO
t
HD,MO
CKPL = 0
CKPL = 1
t
LO/HI
t
LO/HI
1/f
UCxCLK
MSP430G2955
MSP430G2855
MSP430G2755
SLAS800 – MARCH 2013
www.ti.com
USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
f
USCI
USCI input clock frequency
SMCLK, duty cycle = 50% ± 10%
f
SYSTEM
MHz
Maximum BITCLK clock frequency
f
max,BITCLK
3 V
2
MHz
(equals baudrate in MBaud)
(1)
t
τ
UART receive deglitch time
(2)
3 V
50
100
600
ns
(1)
The DCO wake-up time must be considered in LPM3 and LPM4 for baud rates above 1 MHz.
(2)
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see
Figure 22
and
Figure 23
)
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
f
USCI
USCI input clock frequency
SMCLK, duty cycle = 50% ± 10%
f
SYSTEM
MHz
t
SU,MI
SOMI input data setup time
3 V
75
ns
t
HD,MI
SOMI input data hold time
3 V
0
ns
t
VALID,MO
SIMO output data valid time
UCLK edge to SIMO valid, C
L
= 20 pF
3 V
20
ns
Figure 22. SPI Master Mode, CKPH = 0
Figure 23. SPI Master Mode, CKPH = 1
34
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