3.2.1.2 ADC Data Register ADCDATA (Offset 0x0004)
The ADC Data Register contains the converted data value. The output format is two’s complement.
This register is updated if the conversion was initiated with the ADC Conversion Start Register ADCCONV or by
the Automatic Settling Time Control ASTC on the falling edge of ADC_BUSY in the ADC Status Register
(ADCSTAT). Conversions initiated by the sequencer will have no effect to this register.
Bit
Symbol
Description
Access
Reset
Value
31:16
-
Reserved
Write: don't care
Read: always reads as '0'
R
0
15:0
Stores the converted 16 bit data value.
R
0
Table 3-5 : ADC Data Register
Description
±10V
(Gain 1)
±5V (Gain 2)
±2.5V
(Gain 4)
±1.25V
(Gain 8)
Two’s
Complement
Full Scale Range
±10V
±5V
±2.5
±1.25
Least Significant
Bit
305.2μV
152.6μV
76.2μV
38.15μV
FSR - 1LSB
9.999695V
4.999847V
2.499924V
1.249962V
0x7FFF¹
Mi 1LSB
305.2μV
152.6μV
76.2μV
38.15μV
0x0001
Midscale
0V
0V
0V
0V
0x0000
Midscale – 1LSB
-305.2μV
-152.6μV
-76.2μV
-38.15μV
0xFFFF
-FSR + 1LSB
-9.999695V
-4.999847V
-2.499924V
-1.249962V
Full Scale (neg.)
-10V
-5V
-2.5V
1.25V
0x8000²
¹This is also the code for an overrange analog input.
²This is also the code for an underrange analog input.
Table 3-6 : ADC Data Coding
After power up the on board ADC device is in a random state and requires two dummy conversions
before operating correctly. This is based on the chip design of the ADC device.
Software should ignore the data of the first two ADC conversions after power-up.
The software drivers from TEWS TECHNOLOGIES already include these two dummy conversions.
TPMC851 User Manual Issue 1.0.9
Page 16 of 65
