3.2.1 Analog Input Registers
3.2.1.1 ADC Control Register ADCCONT (Offset 0x0000)
Bit
Symbol
Description
Access
Reset
Value
31:12
-
Reserved
Write: don't care
Read: always reads as '0'
R
0
11
RST
ADC Reset
If RST is set to ‘1’, the ADC is reset. Current conversions are aborted.
This bit is cleared immediately after a write access
R/W
0
10
IRQC
IRQ after Conversion Enable
0 = IRQ after Conversion disabled
1 = IRQ after Conversion enabled
An interrupt will be generated after a conversion is finished
(ADC_BUSY changes from 1 to 0).
For pending interrupts and interrupt acknowledge see the ADC Status
Register ADCSTAT.
R/W
0
9
IRQST
IRQ after Settling Time Enable
0 = IRQ after Settling Time disabled
1 = IRQ after Settling Time enabled
An interrupt will be generated after the settling time has elapsed
(SETTL_BUSY changes from 1 to 0)
For pending interrupts and interrupt acknowledge see the ADC Status
Register ADCSTAT.
R/W
0
8
ASTC
Automatic Settling Time Control
0 = OFF (Normal Mode)
A conversion must be initiated manually in the ADC Conversion Start
Register ADCCONV.
1 = ON (Automatic Mode)
A conversion is automatically initiated after the settling time has
elapsed.
The ADC settling time is appr. 16μs.
R/W
0
7:6
GAIN [1:0]
Gain Selection (Analog Input Amplifier)
GAIN1
GAIN0
Gain Factor
Input Voltage Range
0
0
1
±10V
0
1
2
±5V
1
0
4
±2.5V
1
1
8
±1.25V
R/W
00
5
SE/DIFF
Single/Differential Mode Control
0 = Single-ended mode
32 single-ended input channels available
1 = Differential mode
16 differential input channels available
R/W
0
TPMC851 User Manual Issue 1.0.9
Page 14 of 65
