3.2.4 Counter Registers
3.2.4.1 Counter Preload Register CNTPRL (Offset 0x0120)
Bit
Symbol
Description
Access
Reset
Value
31:0
CNTPRL
Counter Preload Register
The value of this register can be loaded into the counter by:
- Setting bit 4 (LCNT) of the Channel Command Register
- An impulse on the Control-Input when the 'Load on Control'-mode is
active
- Automatically in the 'Divide-by-N'-mode every time the counter
creates a borrow or a carry
R/W
0
Table 3-26: Counter Preload Register
3.2.4.2 Counter Compare Register CNTCMP (Offset 0x0124)
Bit
Symbol
Description
Access
Reset
Value
31:0
CNTCMP
Counter Compare Register
Every time the counter matches the Counter Compare Register value,
bit 2 (MAT) of the Channel Status Register is set to '1' and, if enabled, a
Match Interrupt is generated.
R/W
-1
Table 3-27: Counter Compare Register
3.2.4.3 Counter Data Register CNTDATA (Offset 0x0128)
Bit
Symbol
Description
Access
Reset
Value
31:0
CNTDATA
Counter Data Register
This Register contains the actual Counter Data Value.
A Latch Mode event loads the current counter value into the Counter
Data Register. The counter value is latched until the Counter Data
Register is read or when bit 5 (CDLT) of the Channel Status Register is
set to '1'.
R
0
Table 3-28: Counter Data Register
The Counter Data Register will not load again while the latch is active. If a Latch Mode event occurs while the
Counter Data Register Latch is active, the OVFL bit in the Counter Status Register will be set to indicate that data
was lost.
To avoid data inconsistencies this register is developed for a long word (32 bit) read/write access. Byte or
word accesses on this register are not supported and will fail.
TPMC851 User Manual Issue 1.0.9
Page 33 of 65
