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Terasic ALTERA MAX 10 NEEK, User Manual

The Terasic ALTERA MAX 10 NEEK is a versatile development kit that allows users to design and prototype digital systems using the ALTERA MAX 10 FPGA. Enhance your project with the comprehensive User Manual, available for free download from our website. Accelerate your development process with this invaluable resource.

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MAX 10 NEEK

 

120  

www.terasic.com

 

February 4, 2016 

 

Chapter 9

 

 

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Copyright © 2015 Terasic Inc. All rights reserved. 

 

Summary of Contents for ALTERA MAX 10 NEEK

Page 1: ...MAX 10 NEEK User Manual 1 www terasic com February 4 2016...

Page 2: ...10 NEEK Board 10 3 1 Configuration of MAX 10 FPGA on MAX 10 NEEK 10 3 2 Board Status Elements 16 3 3 Clock Circuitry 17 3 4 Peripherals Connected to the FPGA 18 Chapter 4 NEEK10 System Builder 43 4 1...

Page 3: ...9 LCD CAMERA Demonstration 99 Chapter 7 Application Selector 105 7 1 Ready to Run SD Card Demos 105 7 2 Application Selector Details 106 7 3 Running the Application Selector 107 7 4 Creating Your Own...

Page 4: ...ping a wide range of audio video and many other exciting applications The fully integrated kit allows developers to rapidly customize their processor and IP to suit their specific needs rather than co...

Page 5: ...ting materials associated with MAX 10 NEEK including the user manual system builder reference designs and device datasheets Users can download this system CD from the link http cd max10 neek terasic c...

Page 6: ...AX 10 NEEK Board 2 2 1 1 L La ay yo ou ut t a an nd d C Co om mp po on ne en nt ts s Figure 2 1 shows a photograph of the board It depicts the layout of the board and indicates the location of the con...

Page 7: ...I onboard for programming JTAG Mode 256MB DDR3 SDRAM 64Mx16 and 128Mx8 64MB QSPI Flash Micro SD card socket Five push buttons Ten slide switches Ten red user LEDs Two 7 segment displays Three 50MHz cl...

Page 8: ...ADC SMA inputs One 2x10 ADC header with 16 analog inputs connected to MAX10 ADCs 2 2 2 2 B Bl lo oc ck k D Di ia ag gr ra am m o of f t th he e M MA AX X 1 10 0 N NE EE EK K B Bo oa ar rd d Figure 2 3...

Page 9: ...Mx8 512Mb QSPI Flash Micro SD card socket C Co om mm mu un ni ic ca at ti io on n a an nd d E Ex xp pa an ns si io on n H He ea ad de er r Gigabit Ethernet PHY with RJ45 connector UART to USB USB Mini...

Page 10: ...Bu ut tt to on ns s a an nd d I In nd di ic ca at to or rs s Five push buttons Ten slide switches Ten red user LEDs Two 7 segment displays S Se en ns so or rs s Ambient light sensor Humidity and tempe...

Page 11: ...t are used for JTAG configuration with a download cable in the Quartus II software programmer 2 Internal configuration configuration using internal flash Before internal configuration you need to prog...

Page 12: ...he FPGA in JTAG Mode The following shows how the FPGA is programmed in JTAG mode step by step 1 Open the Quartus II programmer and click Auto Detect as circled in Figure 3 2 Figure 3 2 Detect FPGA dev...

Page 13: ...ary 4 2016 Figure 3 3 Select 10M50DAES device 3 FPGA is detected as shown in Figure 3 4 Figure 3 4 FPGA detected in Quartus programmer 4 Right click on the FPGA device and open the sof file to be prog...

Page 14: ...MAX 10 NEEK 13 www terasic com February 4 2016 Figure 3 5 Open the sof file to be programmed into the FPGA device 5 Select the sof file to be programmed as shown in Figure 3 6...

Page 15: ...ic com February 4 2016 Figure 3 6 Select the sof file to be programmed into the FPGA device 6 Click Program Configure check box and then click Start button to download the sof file into the FPGA devic...

Page 16: ...t of the programmer object file pof This configuration data is automatically loaded from the CFM into the MAX 10 devices when the board is powered up Please refer to Chapter 8 Programming the Configur...

Page 17: ...Board Reference LED Name Description D13 5V Power Illuminate when 5V power is active D14 2 5V Power Illuminate when 2 5V power is active D16 1 2V Power Illuminate when 1 2V power is active D6 CONF_DON...

Page 18: ...ted to the clock input of Gigabit Ethernet Transceiver One 24MHz clock signal is connected to the clock inputs of USB microcontroller of USB Blaster II One 28 63636MHz clock signal is connected to the...

Page 19: ...es the interfaces connected to the FPGA User can control or monitor different interfaces with user logic from the FPGA 3 3 4 4 1 1 U Us se er r P Pu us sh h b bu ut tt to on ns s S Sw wi it tc ch he e...

Page 20: ...s set to the UP position a high logic level is generated to the FPGA Figure 3 13 Connections between the slide switches and the MAX 10 FPGA There are also ten user controllable LEDs connected to the F...

Page 21: ...4 Pin Assignment of Slide Switches Signal Name FPGA Pin No Description I O Standard SW 0 PIN_N22 Slide Switch 0 1 5V SW 1 PIN_M22 Slide Switch 1 1 5V SW 2 PIN_N21 Slide Switch 2 1 5V SW 3 PIN_L22 Slid...

Page 22: ...turned on or off by applying a low logic level or high logic level from the FPGA respectively Each segment in a display is indexed from 0 to 6 with corresponding positions given in Figure 3 15 Table...

Page 23: ...power and VCCIO power voltage and current Figure 3 16 shows the connection between the power monitor chip and the MAX 10 FPGA Through the I2C serial interface the power monitor can be configured to m...

Page 24: ...etween the 2x6 TMD header and MAX 10 FPGA Table 3 6 Pin Assignment of 2x6 TMD Header Signal Name FPGA Pin No Description I O Standard GPIO 0 PIN_Y17 GPIO Connection 0 3 3V GPIO 1 PIN_AA17 GPIO Connect...

Page 25: ...PIN_H13 Audio serial data bus data input general purpose input 2 5V AUDIO_SCLK_MFP3 PIN_H14 SPI serial Clock headphone detect output 2 5V AUDIO_SCL_SS_n PIN_F15 I2C Clock SPI interface mode chip sele...

Page 26: ...GA 3 4 7 D DD DR R3 3 M Me em mo or ry y The board supports 256MB of DDR3 SDRAM comprising of one 16 bit 64Mx16 DDR3 device and one 8 bit 128Mx8 device The DDR3 devices shipped with this board are run...

Page 27: ...IN_E20 DDR3 Address 5 SSTL 15 Class I DDR3_A 6 PIN_E21 DDR3 Address 6 SSTL 15 Class I DDR3_A 7 PIN_Y20 DDR3 Address 7 SSTL 15 Class I DDR3_A 8 PIN_C22 DDR3 Address 8 SSTL 15 Class I DDR3_A 9 PIN_D22 D...

Page 28: ...STL 15 Class I DDR3_DQ 11 PIN_N20 DDR3 Data 11 SSTL 15 Class I DDR3_DQ 12 PIN_L20 DDR3 Data 12 SSTL 15 Class I DDR3_DQ 13 PIN_M20 DDR3 Data 13 SSTL 15 Class I DDR3_DQ 14 PIN_M15 DDR3 Data 14 SSTL 15 C...

Page 29: ...Pin No Description I O Standard FLASH_DATA 0 PIN_AB18 FLASH Data 0 3 3V FLASH_DATA 1 PIN_AA19 FLASH Data 1 3 3V FLASH_DATA 2 PIN_AB19 FLASH Data 2 3 3V FLASH_DATA 3 PIN_AA20 FLASH Data 3 3 3V FLASH_DC...

Page 30: ...MII transmit data 0 2 5V NET_TX_D 1 PIN_B12 MII transmit data 1 2 5V NET_TX_D 2 PIN_A13 MII transmit data 2 2 5V NET_TX_D 3 PIN_A14 MII transmit data 3 2 5V NET_RX_DV PIN_A8 GMII and MII receive data...

Page 31: ...7611 is controlled via a serial I2C bus interface which is connected to pins on the MAX 10 FPGA A schematic diagram of the HDMI RX circuitry is shown in Figure 3 23 Detailed information on using the A...

Page 32: ...RX_D23 PIN_V13 Video Pixel Output Port 3 3V HDMI_RX_CLK PIN_P11 Line Locked Output Clock 3 3V HDMI_RX_DE PIN_W10 Data Enable Signal for Digital Video 3 3V HDMI_RX_HS PIN_V12 Horizontal Synchronization...

Page 33: ...l Port Data 3 3V MIPI_PIXEL_D 6 PIN_W3 Parallel Port Data 3 3V MIPI_PIXEL_D 7 PIN_W6 Parallel Port Data 3 3V MIPI_PIXEL_D 8 PIN_W7 Parallel Port Data 3 3V MIPI_PIXEL_D 9 PIN_Y3 Parallel Port Data 3 3V...

Page 34: ...or bridge device 3 3V CAMERA_PWDN_n PIN_R11 Power Down signal of MIPI camera 3 3V CAMERA_I2C_SCL PIN_A20 I2C Clock for MIPI camera 2 5V CAMERA_I2C_SDA PIN_B19 I2C Data for MIPI camera 2 5V 3 3 4 4 1 1...

Page 35: ...3 3V MTL2_HSD PIN_N1 Horizontal Sync Input 3 3V MTL2_VSD PIN_N2 Vertical Sync Input 3 3V MTL2_I2C_SCL PIN_P9 I2C Serial Clock for Touch Screen 3 3V MTL2_I2C_SDA PIN_P10 I2C Serial Data for Touch Scre...

Page 36: ...microphone to be connected to the channel 7 of FPGA ADC2 The output audio signal from on board microphone will be pre amplified by audio operational amplifier OPA1612 then fed into the FPGA ADC Figure...

Page 37: ...nal Name FPGA Pin No Description I O Standard PS2_CLK PIN_V3 PS 2 Clock 3 3V PS2_DAT PIN_P3 PS 2 Data 3 3V PS2_CLK2 PIN_U1 PS 2 Clock reserved for second PS 2 device 3 3V PS2_DAT2 PIN_R3 PS 2 Data res...

Page 38: ...put 3 3V DAC_DATA PIN_A2 Serial Data Input 3 3V 3 4 18 U UA AR RT T t to o U US SB B The board has one UART interface connected for communication with the MAX 10 FPGA This interface doesn t support HW...

Page 39: ...or r The MAX 10 NEEK has a Light to Digital Ambient Light Sensor APDS 9301 that converts light intensity to digital signal output capable of I2C interface with I2C digital interface and programmable...

Page 40: ...s placed at board edge and away from the heat source of MAX 10 NEEK so that user can make ambient temperature measurement without heat interference from the heat source of MAX 10 NEEK Figure 3 32 show...

Page 41: ...EK system CD Figure 3 33 shows the connections between the MAX 10 FPGA and accelerometer Table 3 19 lists the pin assignment of accelerometer to the MAX 10 FPGA Figure 3 33 shows the connections betwe...

Page 42: ...ignals connected between the HPS and Micro SD card socket Table 3 20 lists the pin assignment of Micro SD card socket to the MAX 10 FPGA Figure 3 34 Connections between the MAX 10 FPGA and SD card soc...

Page 43: ...Di is st tr ri ib bu ut ti io on n S Sy ys st te em m The MAX 10 NEEK is powered by Linear Technology s power solution which provides high efficiency power management for FPGAs and SoCs Figure 3 35 sh...

Page 44: ...it the top level design file or place pin assignment The common mistakes that users encounter are Board is damaged due to incorrect bank voltage setting or pin assignment Board is malfunctioned becaus...

Page 45: ...assignment and the I O standard for each user defined I O pin These files can be modified according to the project requirements After the compilation is successful users can download the sof file to t...

Page 46: ...stem Builder is located in the directory Tools SystemBuilder of the NEEK10 System CD Users can copy the entire folder to a host PC without installing the utility After the execution of the NEEK10 Syst...

Page 47: ...e given the flexibility in the System Configuration to include one or more onboard peripherals in the project as shown in Figure 4 4 If a component is enabled the NEEK10 System Builder will automatica...

Page 48: ...uary 4 2016 Figure 4 4 List of onboard peripherals in System Configuration Project Settings The NEEK10 System Builder also provides the option to load a setting or save the current board configuration...

Page 49: ...anage project settings Project Generation When users press the Generate button as shown in Figure 4 6 the NEEK10 System Builder will generate the corresponding Quartus II files and documents as listed...

Page 50: ...ect name v Top level Verilog HDL file for Quartus II 2 Project name qpf Quartus II project file 3 Project name qsf Quartus II setting file 4 Project name sdc Synopsis design constraints file for Quart...

Page 51: ...ould accomplish more sophisticated instructions like setting the sampling rate or resolution which need to transfer two data bytes More information about the PS 2 protocol can be found on various webs...

Page 52: ...sequence in less than 10ms time The transmit data consists of 12bits one start bit as explained before eight data bits one parity check bit odd check one stop bit always one and one acknowledge bit al...

Page 53: ...board Execute the demo batch file ps2_mouse bat under the folder Demonstrations ps2_mouse demo_batch Plug in the PS 2 mouse Press KEY0 to enable data transfer Press KEY1 to clear the display data cac...

Page 54: ...tage measured The power consumption of each bus can be calculated accordingly and switched via SW 2 0 onboard Function Block Diagram Figure 5 2 is the function block diagram of this demonstration The...

Page 55: ...uration file power_monitor sof Demonstration Setup Please make sure Quartus II is installed on the host PC Connect the NEEK10 board J8 to the host PC with USB cable and install the USB Blaster II driv...

Page 56: ...ge and current monitors play a significant role in high reliability system Most of applications can be implemented by an Analog to Digital Converter ADC MAX10 NEEK provides a potentiometer demonstrati...

Page 57: ...nerated by PLL It feeds into the ADC Hard IP in MAX10 device The analog voltage input comes from the VR controls the voltage level The control logic within the ADC Hard IP reads the digitized voltage...

Page 58: ...resistor POT1 with a screwdriver HEX1 and HEX0 will display the voltage value 5 5 4 4 D DA AC C D De em mo on ns st tr ra at ti io on n This demonstration uses the 16 bit Digital to analog converter...

Page 59: ...Demonstrations dac_sma demo_batch Batch file test bat FPGA configuration file dac_sma sof Demonstration Setup Please make sure Quartus II is installed on the host PC Connect the NEEK10 board J8 to th...

Page 60: ...W 2 0 from 000 to 111 and the frequency of the square will be changing The square wave frequency is twice higher When SW 2 0 000 the square wave frequency is at about 2 6KHz When SW 2 0 111 the freque...

Page 61: ...1 is the function block diagram of this demonstration The built in MIC is amplified approximately 392 times via two operational amplifiers The signal is then feed into the ADC of MAX 10 device for con...

Page 62: ..._lcd sof Demonstration Setup Please make sure Quartus II is installed on the host PC Connect the NEEK10 board J8 to the host PC with USB cable and install the USB Blaster II driver Plug in the 5V adap...

Page 63: ...rasic com February 4 2016 Figure 5 13 Figure 5 12 The waveform of onboard MIC is displayed on both LCD and oscilloscope Its sound is played out from the speaker Figure 5 13 LEDR0 9 displays the volume...

Page 64: ...ecessary where HDMIConfig I2C module is used to configure the ADV7611 chip This demo uses the Video and Image Processing VIP IP provided by Altera which requires specific video data format Avalon ST V...

Page 65: ...dio memory Table in Figure 5 15 From the Audio memory Table it can be seen the data is 0100 at 00 2 position This means it will configure the Audio Codec Address 0x01 register the first 2bit to 0x00 t...

Page 66: ...ion file hdmi_rx_lcd sof Demonstration Setup Make sure both Quartus II and USB Blaster II driver are installed on your PC Use a HDMI DVD player and use HDMI cable to connect the MAX 10 NEEK to the pla...

Page 67: ...ill show the video One thing to note is that we do not provide the HDCP KEY and this would cause issues to some specific high resolution video which not being able to play correctly Therefore in that...

Page 68: ...er r M Mo on ni it to or r The power monitor demo shows how to measure the power consumed through the onboard power monitor chip LTC2990 There are three LTC2990 to monitor the following power rails 3...

Page 69: ...for each power rail A current sense resistor RSENSE is added to the path of each power rail LTC2990 measures the voltage difference V1 V2 and calculate the current based on the formula below Current V...

Page 70: ...ntent is renewed and cleared i e 0 when the register content is accessed Bit 6 of the MSB register is the sign bit Bit 5 through 0 represent the result of bits D 13 8 in two s complement conversion Th...

Page 71: ...e voltage difference registers to make sure the measurement is finished and register values is the latest for reading Figure 6 5 tatus register of LTC2990 Design Tools Quartus II v15 0 64 bit Nios II...

Page 72: ...configuration file power_monitor_nios sof Nios batch file test sh NIOS program nios_app elf Demonstration Setup Please follow the procedures below to set up the demonstration Please make sure Quartus...

Page 73: ...o enable the communication between the FPGA and the host computer In this demonstration we will show you how to control the LEDRs by sending a command on the computer putty terminal The command is sen...

Page 74: ...enu of Nios II Eclipse D De em mo on ns st tr ra at ti io on n B Ba at tc ch h F Fi il le e Demo Batch File Folder uart_usb demo_batch The demo batch file includes following files Batch Files uart_usb...

Page 75: ...owing website http www ftdichip com Drivers VCP htm Open the Device Manager to ensure which common port is assigned to the UART to USB port as shown in Figure 6 9 The common number 9 COM9 is assigned...

Page 76: ...file folder uart_usb demo_batch The result of Nios II terminal and putty terminal is shown in Figure 6 11 Figure 6 11 Running Result of Uart_USB Demo In the putty terminal type any character to change...

Page 77: ...shows the hardware block diagram of this demonstration The system requires a 50 MHz clock provided from the board The PLL generates a 100MHz clock for Nios II processor and the other controllers The a...

Page 78: ...s FAT16 FAT32 file system for reading wave files that are stored in the SD Card In this block only read function is implemented The WAVE Lib block implements WAVE file decoding function for extracting...

Page 79: ...the main program reads 512 byte audio data from the SD Card and then writes the data to DAC FIFO in the Audio Controller Before writing the data to the FIFO the program will verify if the FIFO is ful...

Page 80: ...ed wave files must have a sample rate of the following options 96K 48K 44 1K or 8K In addition the wave files must be stereo and 16 bits per channel Connect a headset or speaker to the MAX 10 NEEK boa...

Page 81: ...M for hardware verification The DDR3 SDRAM controller handles the complex aspects of using DDR3 SDRAM by initializing the memory devices managing SDRAM banks and keeping the devices refreshed at appro...

Page 82: ...ding data to from the SDRAM When verification process is completed the result is displayed in the JTAG Terminal Altera DDR3 SDRAM Controller with UniPHY To use Altera DDR3 controller you need to perfo...

Page 83: ...os sof Nios II Program ddr3_nios elf Demonstration Setup Please follow the procedures below to set up the demonstration Make sure Quartus II and Nios II are installed on your PC Power on the MAX 10 NE...

Page 84: ...an continuously listen for commands on a TCP IP port and operate the MAX 10 NEEK LEDs according to the commands from the telnet client As Part of the Nios II EDS NicheStack TCP IP Network Stack is a c...

Page 85: ...ns Nios II processor DDR3 memory JTAG UART timer Triple Speed Ethernet Scatter Gather DMA controller and other peripherals etc In the Core Configuration Tab of the Altera Triple Speed Ethernet Control...

Page 86: ...a 100MHz clock source is expected to divide the MAC control register interface clock to produce the MDC clock output on the MDIO interface The MAC control register interface clock frequency is 100MHz...

Page 87: ...NEEK 86 www terasic com February 4 2016 Figure 6 21 Qsys Builder Figure 6 22 shows the connections for programmable 10 100 1000Mbps Ethernet operation via RGMII Figure 6 22 PHY connected to the MAC vi...

Page 88: ...anagement Figure 6 23 Nios II Software Routine Architecture Finally the detailed descriptions for Software flow chart of the Socket Server program are listed below Firstly the Socket Server program in...

Page 89: ...rations socket_server demo_batch Batch file socket_server bat FPGA configure file socket_server sof Application file folder socket_server demo_batch Application file open_telnet bat Demonstration Setu...

Page 90: ...imple Socket Server To establish connection start the telnet client session by executing open_telnet bat file and include the IP address assigned by the DHCP server provided IP along with the port num...

Page 91: ...he Multi touch LCD module based on Altera Qsys tool and the Video and Image Processing VIP suite It demonstrates how to use multi touch gestures and resolution The GUI of this demonstration is control...

Page 92: ...MAX 10 NEEK 91 www terasic com February 4 2016 Figure 6 27 GUI of Painter Demo Figure 6 28 shows the single finger painting of canvas area Figure 6 28 Single Finger Painting...

Page 93: ...MAX 10 NEEK 92 www terasic com February 4 2016 Figure 6 29 shows the zoom in gesture Figure 6 29 Zoom In Gesture Figure 6 30 shows the 5 Point painting of canvas area Figure 6 30 5 Point Painting...

Page 94: ...y the Nios II processor according to user input For multi touch processing whenever there is any touch activity occurring a I2C Controller IP is used to retrieve serial data from the I2C interface the...

Page 95: ...cc ce el le er ro om me et te er r D De em mo on ns st tr ra at ti io on n This demonstration shows a bubble level implementation based on a digital accelerometer We use I2 C protocol to control the...

Page 96: ...sor_lightsensor_lcd demo_batch The demo batch file includes the following files Batch File gsensor_lightsensor_lcd bat gsensor_lightsensor_lcd sh FPGA Configure File gsensor_lightsensor_lcd sof Nios I...

Page 97: ...Te em mp pe er ra at tu ur re e S Se en ns so or r This demonstration illustrates steps to evaluate the performance of humidity and temperature sensor HDC1000 The HDC1000 is a fully integrated humidit...

Page 98: ...measurement resolution can be set to 8 11 or 14 bits for humidity 11 or 14 bits for temperature Different resolution setting results in a different conversion time When triggering the measurements op...

Page 99: ...ow the procedures below to set up the demonstration Make sure Quartus II and USB Blaster II driver are installed on your PC Connect the USB cable to the USB Blaster II connector J8 on the MAX 10 NEEK...

Page 100: ...m format and feeds it to Altera VIP The other IP developed by Terasic for auto focus is used to find the optimized focus settings of user defined image area S Sy ys st te em m B Bl lo oc ck k D Di ia...

Page 101: ...ure the camera module including OV8865 image sensor and VCM149C The second I2C controller is used to configure the MIPI Bridge IC TC358748XBG The third I2C controller is used to retrieve the touch inf...

Page 102: ...tration Figure 6 37 Camera demo running on MAX 10 NEEK board A Five fingers touch function is implemented in this demonstration to stop LCD from refreshing the camera image This is achieved by stoppin...

Page 103: ...gure 6 38 shows the Five fingers touch to stop the camera video Figure 6 38 Five fingers touch to stop the camera video Figure 6 39 shows the zoom in or zoom out gesture with two fingers Figure 6 39 T...

Page 104: ...tus II v15 0 Nios II Eclipse 15 0 Demonstration Source Code Quartus project directory lcd_camera Nios II Eclipse project workspace lcd_camera software D De em mo on ns st tr ra at ti io on n B Ba at t...

Page 105: ...en installed on the host PC Execute the demo batch file lcd_camera bat under the batch file folder lcd_camera demo_batch The LCD panel will start showing the video captured from the camera Use two poi...

Page 106: ...can find several ready to run demos in your micro SD card root directory as well as in the System CD under Factory_Recovery SD_content folder Figure 7 1 shows the photograph of the application selecto...

Page 107: ...the DDR3 The SG DMA reads the data and translates it to the VGA controller through the Avalon Streaming interface The I2C controller and the PIO Controller are implemented to get the touch action data...

Page 108: ...e el le ec ct to or r Connect power to the MAX 10 NEEK Insert the micro SD card with applications into the micro SD Card socket of MAX 10 NEEK Make sure the CONFIG_SEL switch is set to 0 and Switch on...

Page 109: ...ce of the Nios II CPU Set the CPU reset vector and exception vector to the QSPI flash zone with offset 0 as shown in Figure 7 4 Figure 7 4 NiosII CPU Vectors Setting The configuration mode in Quartus...

Page 110: ...rogramming File In the project directory you will find the generated file test pof and test_auto rpd The rpd file is the raw program data file which is been written into the onchip flash Copy the appl...

Page 111: ...the elf into a hex file On your host PC launch a Nios II Command Shell from Start Programs Altera Nios II version EDS Nios II Command Shell From the command shell navigate to where your elf file is lo...

Page 112: ...ctor project is placed in Demonstrations application_selector Power on the MAX 10 NEEK board with the USB cable connected to the UBII J8 port Download the max10_qpfl sof to the board Press Auto Detect...

Page 113: ...on nf fi ig gu ur ra at ti io on n The internal configuration scheme for all MAX 10 devices except for 10M02 device consists of the following mode Dual Compressed Images configuration image is stored...

Page 114: ...ows 1 After powering up the device samples the BOOT_SEL pin to determine which application configuration image to boot The BOOT_SEL pin setting can be overwritten by the input register of the remote s...

Page 115: ...need this feature skip this section Two main steps are necessary for a project support dual configuration mode Add dual configuration IP Modify Configuration Mode in device setting A Dual Configurati...

Page 116: ...d Pin Options and choose Dual Compressed Images in configuration table as shown in Figure 8 5 Then compile the project to generate the sof file Figure 8 5 Set Dual Configuration Modes These procedures...

Page 117: ...lick generate button to generate the object file dual_boot pof Figure 8 7 Add Sof Files The final step is to download the pof into MAX10 FPGA Open the programmer tool and add the dual_boot pof as show...

Page 118: ...ing The onchip flash memory in the FPGA provides the possibility to boot the software for the Nios II processor The demonstration my_first_niosII is designed for Nios II processor loading software aft...

Page 119: ...in Eclipse as shown in Figure 8 11 Figure 8 11 Make Target Setting After clicking build button a onchip_flash hex file will be generated in the path software software_project mem_init Open the convert...

Page 120: ...grammer tool and add the pof generated above to download into the onchip flash Power cycle the board the Nios II software will be running after the image has been loaded The Nios II processor can also...

Page 121: ...com February 4 2016 Chapter 9 Appendix R Re ev vi is si io on n H Hi is st to or ry y Version Change Log V1 0 Initial Version C Co op py yr ri ig gh ht t S St ta at te em me en nt t Copyright 2015 Ter...

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