MAX 10 NEEK
100
www.terasic.com
February 4, 2016
The settings by default are:
Resolution : 800x480 (LCD resolution)
Frame Rate: 60 fps
Pixel Data: RAW10
Bin Mode: 1, 2, 4 (achieved ZOOM-IN/ ZOOM-OUT function)
Users can change the settings base on their requirements.
A MIPI CSI-2 bridge chip TC358748XBG is used to decode the video data via MIPI interface from
the camera module to the FPGA in parallel. The camera module is configured as RAW10 in this
demonstration, so the data width of 24-bit parallel bus between MIPI CSI-2 bridge and FPGA is
only 10-bit used.
For image process in FPGA, the reference design is developed based on Altera’s Video and Image
Processing (VIP) suite. The Terasic Camera IP translates the parallel Bayer pattern data into RGB
data to meet the specification of Altera VIP video streaming. The Frame Buffer from VIP is used for
buffering image data in DDR3 and matching the frame rate from Terasic camera IP to the Clock
Video Output of VIP. It displays the final 800x480 RGB frame image on the LCD panel. The
auto-focus IP by Terasic can be used to get a better image quality by finding the optimized focus
setting.
The Nios II program running on on-chip memory controls three I2C controllers to configure the
image sensor, motor driver, MIPI CSI-2 Bridge IC, and touch device. First I2C controller is used to
configure the camera module, including OV8865 image sensor and VCM149C. The second I2C
controller is used to configure the MIPI Bridge IC TC358748XBG. The third I2C controller is used
to retrieve the touch information from the touch device.
For better image quality with user-defined area focused, a simple auto-focus algorithm is used and
implemented as a Qsys IP. The range of motor position, which controls the focus, is defined as 0 ~
1023. The algorithm searches for the best focus position in two stages. It takes images when the
focus position is set to 0, 6, 12 .. etc. in the first stage and calculates the contrast of these images to
narrow down the search by finding the most clear image of all at focus position X. It then starts to
take images again when the focus position is set to X-3, X-2, X-1, X, X+1, X+2, and X+3 in the
second stage to come up with the best focus position after two iterations. The Nios II processor is
used to configure and trigger the IP. Users can develop and implement a more efficient algorithm
based on the auto-focus IP provided in this demonstration.
Note: The focus driver IC (VCM149C) in the camera module is configured by the Terasic
auto-focus IP through its own I2C master controller. The image sensor in the camera module is also
configured through the same I2C bus by its own I2C master controller. The arbitration is
implemented in the Nios II program to prevent the I2C bus occupied by the two I2C master
controllers simultaneously. Users must make sure there is only one I2C master used at the same one
