MAX 10 NEEK
37
www.terasic.com
February 4, 2016
interfaces. The analog voltage output of DAC8551 is connected to a SMA connector.
Figure 3-27
shows the connection between DAC and MAX 10 FPGA. The pin assignment associated to this
DAC is shown in
Table 3-15.
Figure 3-29 Connection between DAC and MAX 10 FPGA
Table 3-15 Pin Assignment of DAC
Signal Name
FPGA Pin No.
Description
I/O Standard
DAC_SYNC_n
PIN_B2
Frame Sync Signal for Input Data
3.3V
DAC_SCLK PIN_B1
Serial Clock Input
3.3V
DAC_DATA
PIN_A2
Serial Data Input
3.3V
3.4.18
U
U
A
A
R
R
T
T
t
t
o
o
U
U
S
S
B
B
The board has one UART interface connected for communication with the MAX 10 FPGA. This
interface doesn’t support HW flow control signals. The physical interface is implemented by
UART-USB onboard bridge from a FT232R chip to the host with an USB Mini-B connector. More
information about the chip is available on the manufacturer’s website, or in the directory
\Datasheets\UART TO USB of MAX 10 NEEK system CD.
Figure 3-30
shows the connections
between the MAX 10 FPGA, FT232R chip, and the USB Mini-B connector.
Figure 3-34
lists the
pin assignment of UART interface connected to the MAX 10 FPGA.
