MAX 10 NEEK
18
www.terasic.com
February 4, 2016
Table 3-2
Pin Assignment of Clock Inputs
Signal Name
FPGA Pin No.
Description
I/O Standard
MAX10_CLK1_50 PIN_N5
50
MHz clock input
2.5V
MAX10_CLK2_50 PIN_V9
50
MHz clock input
3.3V
MAX10_CLK3_50 PIN_N14
50
MHz clock input
1.5V
ADC_CLK_10 PIN_M9
10
MHz clock input
3.3V
3
3
.
.
4
4
P
P
e
e
r
r
i
i
p
p
h
h
e
e
r
r
a
a
l
l
s
s
C
C
o
o
n
n
n
n
e
e
c
c
t
t
e
e
d
d
t
t
o
o
t
t
h
h
e
e
F
F
P
P
G
G
A
A
This section describes the interfaces connected to the FPGA. User can control or monitor different
interfaces with user logic from the FPGA.
3
3
.
.
4
4
.
.
1
1
U
U
s
s
e
e
r
r
P
P
u
u
s
s
h
h
-
-
b
b
u
u
t
t
t
t
o
o
n
n
s
s
,
,
S
S
w
w
i
i
t
t
c
c
h
h
e
e
s
s
,
,
L
L
E
E
D
D
s
s
The board has five push-buttons connected to the FPGA, as shown in
Figure 3-11.
MAX 10 devices
support Schmitt trigger input on all I/O pins. A Schmitt trigger feature introduces hysteresis to the
input signal for improved noise immunity, especially for signal with slow edge rate and act as
switch debounce in
Figure 3-12
for the push-buttons connected.
Figure 3-11 Connections between the push-buttons and the MAX 10 FPGA
