MAX 10 NEEK
85
www.terasic.com
February 4, 2016
In the MAC Options tab (See
Figure 6-20
), users should set up proper values for the PHY chip
88E1111. The MDIO Module should be included, as it is used to generate a 2.5MHz MDC clock for
the PHY chip from the controller's source clock(here a 100MHz clock source is expected) to divide
the MAC control register interface clock to produce the MDC clock output on the MDIO interface.
The MAC control register interface clock frequency is 100MHz and the desired MDC clock
frequency is 2.5MHz, so a host clock divisor of 40 should be used.
Figure 6-20 MAC Options Configuration
Once the Triple-Speed Ethernet IP configuration has been set and necessary hardware connections
have been made as shown in
Figure 6-21
, click on generate.
