MAX 10 NEEK
36
www.terasic.com
February 4, 2016
websites. The pin assignment associated to this interface is shown in
Figure 3-28
.
Note: If users connect only one PS/2 equipment, the PS/2 signals connected to the FPGA I/O
should be “PS2_CLK” and “PS2_DAT”.
Figure 3-27 Connections between the MAX 10 FPGA and PS/2
Figure 3-28 Y-Cable for using keyboard and mouse simultaneously
Table 3-14 Pin Assignment of PS/2
Signal Name
FPGA Pin No.
Description
I/O Standard
PS2_CLK PIN_V3 PS/2
Clock
3.3V
PS2_DAT PIN_P3 PS/2
Data
3.3V
PS2_CLK2
PIN_U1
PS/2 Clock (reserved for second PS/2 device) 3.3V
PS2_DAT2
PIN_R3
PS/2 Data (reserved for second PS/2 device) 3.3V
3.4.17
D
D
i
i
g
g
i
i
t
t
a
a
l
l
-
-
t
t
o
o
-
-
A
A
n
n
a
a
l
l
o
o
g
g
C
C
o
o
n
n
v
v
e
e
r
r
t
t
e
e
r
r
(
(
D
D
A
A
C
C
)
)
The board provides a Texas Instruments DAC8551 16-bit digital-to-analog converter (DAC). It is a
small, low power, voltage output DAC. The DAC8551 used a versatile 3-wire serial interface that
operates at clock rates to 30MHz and is compatible with standard SPI, QSPI, Microwire and DSP
