External Controllers and Printers
ST112 SONET Transmission Test Set
6–13
Table 6–9 Status Byte Register Bit Definitions
Bit Definition
7 (MSB)
Not defined.
6 MSS
1
(Master Status Summary): This bit summarizes the state of the three other bits in
the SBR. It is set to 0 if all other bits are 0. It will be set to 1 when any other bit in the
SBR equals 1 and its corresponding bit in the SRER is set to one. The status of the
MSS bit is reevaluated each time a bit in the SBR or the Service Request Enable
Register (SRER) changes.
5
ESB (Event Status Bit): This bit summarizes the Standard Event Status Register
(SESR). It is set to 0 if all bits in the SESR are 0. It is set to 1 if any enabled bit in the
SESR equals 1. If the ESB is enabled and set to 1, then the RQS and MSS bits will be
set to 1. The status of the ESB bit is reevaluated each time one of the bits in the SESR
or the Event Status Enable Register (ESER) changes.
4
MAV (Message Available): This bit is set to 1 when there is an output available for the
controller.
0 - 3
Not defined.
1
When you use a serial poll to read the SBR, bit 6 is the RQS bit. When you use the *STB?
query to read the SBR, bit 6 is the MSS bit.
Service Request Enable Register
The Service Request Enable Register (SRER) is the enable register associated with the SBR
status register defined above. The SRER contains an enable bit for the ESB and MAV bits in the
SBR. However there is no enable bit for the MSS or RQS bits which are always enabled.
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