Tektronix 7623, Instruction Manual

Page: 58 / 266

Circuit Description-7623/R7623 Service
HI, the right vertical unit is displayed and when it switches
to LO, the left vertical unit is displayed.
Alt. In the ALT mode, the VERT MODE switch applies
a HI level to the anodes of diodes CR130-CR155 through
R130. These diodes are forward biased so the Display Right
Command from pin 5 of U156A can pass to the emitter of
Q132 to determine the Mainframe Vertical Mode Command
level. The Display Right Command switches between its HI
and LO levels at a rate determined by the Vertical Binary
stage.
Add and Left. The control levels in the ADD and LEFT
positions of the VERT MODE switch are not connected to
this stage. However, since only the line corresponding to
the selected vertical mode can be HI, the RIGHT, CHOP,
and ALT lines must remain at their LO level when either
LEFT or ADD are selected. Therefore, the emitter of Q132
remains LO to produce a LO Mainframe Vertical Mode
Control output level. Final control of LEFT or ADD mode
is made by the Vertical Interface circuit.
A logic diagram of the Vertical Mode Control stage is
shown in Fig. 3-9. The discrete components which make up
each logic function are identified. The gate connected to
the input of the Vertical Mode Buffer Amplifier is a
phantom-OR gate. A phantom-OR gate performs the OR
logic
function merely by interconnection of the three
inputs.
Vertical Binary
The Vertical Binary stage consists of integrated circuit
U156A and transistor Q150. U156A is a D-type flip-flop
with direct-set and direct-clear inputs (see Table 3-1 for
operating details). The connection between the "0" output
and the data (D) input enables this flip-flop to operate in
the triggered mode. A logic diagram of the Vertical Binary
stage is shown in Fig. 3-10.
The operation of the Vertical Binary stage is controlled
by the level of the ALT Mode line from the VERT MODE
switch. When this switch is set to ALT, a HI level is
connected to the emitter of Q150 through R152. This HI
level disables Q150 so its collector remains HI. As a result,
Q150 has no effect upon operation of the Vertical Binary
stage and the direct-clear input of U156A remains HI so it
does not affect the operation of U156A. Therefore, U156A
operates as a basic triggered flip-flop which changes output
states with each positive-going Sweep Holdoff pulse at the
trigger (T) input. The Sweep Holdoff pulse goes positive at
the end of each sweep. The signal at the "1" output of
U156A switches between the HI and LO level at one-half
the rate of the Sweep Holdoff signal from the horizontal
plug-in unit. Fig. 3-11 shows the time relationship between
the input and output signals for this stage, and gives the
resultant display with each signal combination.
For any other position, the emitter of Q150 is pulled LO
by the ALT Mode command from the VERT MODE
switch. This enables Q150, but it does not change output
state unless the level at the "1" output of U156A is HI.
Quiescently, the output of Q150 is LO. Therefore, when
the positive-going Sweep Hold-off pulse is received at the
end of the sweep, the "1" output of U156A goes HI. This
activates Q150 and its output goes LO to provide a
direct-clear reset to U156A. The "1" output of U156A is
reset to its LO level, and Q150 is again disabled so its
output returns to the HI level. The stage is now ready for
From
VERT
MODE
switch
Mainframe
Vertical
Mode
Command
Fifl. 3-9. Logic diagram of Vertical Mode Control and Vertical Mode Buffer Amplifier stages.
3-14