Technosoft iPOS4808 MX Series, Technical Reference

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
Technosoft 2014 29 iPOS4808 MX Technical Reference
Logic “HIGH”; Internal 4.7K 
pull-up to +3.3
0 0 0
Lo
gic “HIGH”; Pulled to +5V
0.15 0.2
Logic “HIGH”; Pulled to +24V
2 2.5
Input frequency 0 150 KHz
Minimum pulse width 3.3 µS
ESD protection Human body model ±5 KV
2.5.9. Digital Outputs (OUT0, OUT1, OUT2/Error, OUT3/ Ready, OUT5)
Min. Typ. Max. Units
Mode compliance
All outputs (OUT0, OUT1, OUT2/Error,
OUT3/Ready) TTL / CMOS / Open-collector /
NPN 24V
Ready, Error Same as above + LVTTL (3.3V)
Default state
Not supplied (+V
LOG
floating or to GND) High-Z (floating)
Immediately
after power-up
OUT0, OUT1, OUT5
Logic “HIGH”
OUT2/Error, OUT3/ Ready
Logic “LOW”
Normal
operation
OUT0, OUT1, OUT2/Error,
OUT5
Logic “HIGH”
OUT3/Ready
Logic “LOW”
Output voltage
Logic “LOW”; output current = 0.5A
0.2 0.8
V
Logic “HIGH”;
output current
= 0, no load
OUT2/Error, OUT3/ Ready 2.9 3 3.3
OUT0, OUT1 4 4.5 5
Logic “HIGH”, external load to +V
LOG
V
LOG
Absolute maximum, continuous -0.5 V
LOG
+0.5
Absolute maximum, surge (duration

1S)
†
-1 V
LOG
+1
Output current
Logic “LOW”, sink curren
t, continuous 0.5 A
Logic “LOW”, sink current, pulse ≤
5 sec. 1 A
Logic “HIGH”, source
current; external load
to GND; V
OUT
>= 2.0V
OUT2/Error,
OUT3/ Ready
2 mA
OUT0, OUT1 4 mA
Logic “HIGH”, leakage current; external
load to +V
LOG
; V
OUT
= V
LOG
max = 40V
0.1 0.2 mA
Minimum pulse width 2 µS
ESD protection Human body model ±5 KV
2.5.10. Digital Hall Inputs (Hall1, Hall2, Hall3)
Min. Typ. Max. Units
Mode compliance TTL / CMOS / Open-collector
Default state Input floating (wiring disconnected) Logic HIGH
Input voltage
Logic “LOW”
0 0.8 V