BIOS User's Manual
5-10
data back to DRAM system memory will resolve the
problem. Most DRAM errors are soft errors. If a hard
(uncorrectable) error occurs, writing the fixed data
back to DRAM system memory does not solve the
problem. In this case, the second time the error
occurs in the same location, a Parity Error is reported,
indicating an uncorrectable error. If ECC is selected,
AMIBIOS automatically enables the System
Management Interface (SMI). If you do not want to
enable power management, set the Power
Management/APM option to
Disabled
and set all
Power Management Setup timeout options to
Disabled
. To enable power management, set Power
Management/APM to
Enabled
and set the power
management timeout options as desired.
DRAM Refresh Rate
This option specifies the interval between Refresh signals to DRAM
system memory. The settings for this option are
15.6 us
(micro-sec-
onds),
31.2 us
,
62.4 us
,
124.8 us
or
249.6 us
.
Memory Hole
This option specifies the location of an area of memory that cannot be
addressed on the ISA bus. The settings are
Disabled
,
15 MB
-
16 MB
, or
512 KB
-
640 KB
.
SDRAM CAS# Latency
This option regulates the column address strobe. The settings are 2
SCLKs, 3 SCLKs or
Auto
.
SDRAM RAS# to CAS# Delay
This option specifies the length of the delay inserted between the RAS
and CAS signals of the DRAM system memory access cycle if SDRAM is
installed. The settings are
Auto
(AMIBIOS automatically determines the
optimal delay),
2 SCLKs
or
3 SCLKs
.
Note: The Optimal default
setting is Auto and the Fail-Safe default setting is 3 SCLKs
.
SDRAM RAS# Precharge
This option specifies the length of the RAS precharge part of the DRAM
system memory access cycle when Synchronous DRAM system memory
is installed in the computer. The settings are
Auto
(AMIBIOS automatically
Summary of Contents for SUPER P6DBE
Page 12: ...Chapter 1 Introduction 1 3 Notes...
Page 38: ...Chapter 1 Introduction 1 29...
