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UPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA/P6SBM

Manual

1-12

SUPER P6SBS

Figure 1-9. SUPER P6SBS Motherboard Image

Summary of Contents for SUPER P6DBE

Page 1: ...SUPER P6DBS SUPER P6DBE SUPER P6DBU SUPER P6SBU SUPER P6SBS SUPER P6SBA SUPER P6SBM USER S AND BIOS MANUAL Revision 2 5 SUPER...

Page 2: ...chine without prior written consent IN NO EVENT WILL SUPERMICRO COMPUTER BE LIABLE FOR DIRECT INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING FROM THE USE OR INABILITY TO USE THIS PRODUCT...

Page 3: ...the chipset and offers warranty information Refer to Chapter 2 Installation for instructions on how to install the Pentium II processor the retention mechanism and the heat sink support This chap ter...

Page 4: ...r Standard Setup Advanced Setup Chipset function Power Management PCI PnP Setup and Peripheral Setup Appendix A offers information on BIOS error beep codes and messages Appendix B shows post diagnosti...

Page 5: ...U Motherboard Layout 1 11 SUPER P6SBS Image 1 12 SUPER P6SBS Motherboard Layout 1 13 SUPER P6SBA Image 1 14 SUPER P6SBA Motherboard Layout 1 15 SUPER P6SBM Image 1 16 SUPER P6SBM Motherboard Layout 1...

Page 6: ...Secondary Power Connector 2 8 Infrared Connector 2 8 PW_ON Connector 2 9 Reset Connector 2 9 Hard Drive LED 2 9 Keylock Power LED Connector 2 9 Speaker Connector 2 10 Power Save State Select 2 10 ATX...

Page 7: ...n Summary Screen 4 3 AMIBIOS Setup 4 3 Chapter 5 Running Setup 5 1 Setup 5 1 5 1 1 Standard Setup 5 1 5 1 2 Advanced Setup 5 3 5 1 3 Chipset Setup 5 7 5 1 4 Power Management 5 13 5 1 5 PCI PnP Setup 5...

Page 8: ...ED 1 9 CPU 1 Fan 2 11 CPU 2 Fan 2 11 Thermal Control Fan 2 11 Wake on LAN 2 11 External Thermal Input 1 9 1 2 sensor 1 3 4 sensor 3 Jumpers JB1 JB2 JB3 JB4 JBT1 JP20 S TERM JOH JPS1 BZ ON JP11 J36 Con...

Page 9: ...anual Front Control Panel Connector Please see pages 2 9 and 2 10 for pin definitions Hard Drive LED Keyboard lock Speaker IR Com Power LED Power On Reset JF1 JF2 X X Hard Drive LED Keyboard lock Spea...

Page 10: ...slot and the SUPER P6SBM has 3 PCI and 1 ISA with one shared slot All seven motherboards have the AGP port and all but the P6SBM can accommodate a total of 1 GB EDO at 66 MHz or 512 MB unbuffered SDR...

Page 11: ...on board Adaptec 7895 MultiChannel UW SCSI controller The dual chan nels allow a data transfer rate of 40 MB s per channel Additionally these two motherboards have a RAID port on board to support the...

Page 12: ...Chapter 1 Introduction 1 3 Notes...

Page 13: ...SUPER P6DBS P6DBE P6DBU P6SBU P6SBS P6SBA P6SBM Manual 1 4 SUPER P6DBS Figure 1 1 SUPER P6DBS Motherboard Image...

Page 14: ...CSI Manufacturer Settings JBT1 1 2 default 2 3 CMOS Clear To clear the CMOS completely disconnect the power source JL1 OFF default ON intrusion JP11 1 2 Auto 2 3 66 MHz OFF 100 MHz JP20 1 2 PIIX CTL P...

Page 15: ...SUPER P6DBS P6DBE P6DBU P6SBU P6SBS P6SBA P6SBM Manual 1 6 SUPER P6DBE Figure 1 3 SUPER P6DBE Motherboard Image...

Page 16: ...urer Settings JBT1 1 2 default 2 3 CMOS Clear To clear the CMOS completely disconnect the power source JL1 OFF default ON intrusion JP11 1 2 Auto 2 3 66 MHz OFF 100 MHz JP20 1 2 PIIX CTL PD State 2 3...

Page 17: ...SUPER P6DBS P6DBE P6DBU P6SBU P6SBS P6SBA P6SBM Manual 1 8 SUPER P6DBU Figure 1 5 SUPER P6DBU Motherboard Image...

Page 18: ...completely disconnect the power source JL1 OFF default ON intrusion JP11 1 2 Auto 2 3 66 MHz OFF 100 MHz JP20 1 2 PIIX CTL PD State 2 3 BIOS CTL PD State default WOL Wake on LAN S TERM On SCSI Termin...

Page 19: ...SUPER P6DBS P6DBE P6DBU P6SBU P6SBS P6SBA P6SBM Manual 1 10 SUPER P6SBU Figure 1 7 SUPER P6SBU Motherboard Image...

Page 20: ...gs JBT1 1 2 default 2 3 CMOS Clear To clear the CMOS completely disconnect the power source JL1 OFF default ON intrusion JP11 1 2 Auto 2 3 66 MHz OFF 100 MHz JP20 1 2 PIIX CTL PD State 2 3 BIOS CTL PD...

Page 21: ...SUPER P6DBS P6DBE P6DBU P6SBU P6SBS P6SBA P6SBM Manual 1 12 SUPER P6SBS Figure 1 9 SUPER P6SBS Motherboard Image...

Page 22: ...hermal Control Fan JA5 JA6 SCSI Termination 1 JTM 1 WOL BT2 BATTERY Chassis Intrusion JL1 JBT2 JBT1 1 1 JB1 JB4 SCSI LED JP11 JBT1 CMOS Clear JBT2 Ext Battery Manufacturer Settings JBT1 1 2 default 2...

Page 23: ...SUPER P6DBS P6DBE P6DBU P6SBU P6SBS P6SBA P6SBM Manual 1 14 SUPER P6SBA Figure 1 11 SUPER P6SBA Motherboard Image...

Page 24: ...JL1 Chassis Intrusion JBT1 CMOS Clear JBT2 Ext Battery JP11 U9 CPU FAN JT1 1 J34 PS 2 KB PS 2 MOUSE S UPER P6SBA PCI 2 Manufacturer Settings JBT1 1 2 default 2 3 CMOS Clear To clear the CMOS complete...

Page 25: ...SUPER P6DBS P6DBE P6DBU P6SBU P6SBS P6SBA P6SBM Manual 1 16 SUPER P6SBM Figure 1 13 SUPER P6SBM Motherboard Image...

Page 26: ...JBT1 CMOS Clear BZ1 JT2 PIIX4E BX J 1 9 Parallel Port JB1 JB2 JB3 JB4 JBT1 JP20 1 JL1 J36 J8 JJ14 1 9 6 8 050 J4 J5 J6 BATTERY J P 1 2 JT3 BT2 U27 JPWAKE 1 1 Manufacturer Settings JBT1 1 2 default 2...

Page 27: ...RAM Host Bus PCI Slots SMBus USB Ports USB IDE Ports ISA Slots BIOS SIO SCSI Figure 1 15 440BX AGP SET System Block Diagram Dual Processors NOTE This is a general block diagram and may not represent t...

Page 28: ...en the CPU bus is running at 100 MHz the SDRAM must be PC 100 compliant DIMMs Note The maximum memory cacheability size depends on the processor capabilities Error Checking and Correction and Error Ch...

Page 29: ...ctor P6DBU P6SBU only 68 pin 16 bit Dual Ultra Wide SCSI connectors and 50 pin 8 bit Ultra SCSI connector P6DBS P6SBS only RAID port for Adaptec ARO 1130xA RAIDport II card P6DBS P6SBS only RAID port...

Page 30: ...nd is based on a set of performance enhancements to PCI The I O subsystem portion of the 440BX platform is based on the PIIX4E a highly integrated version of Intel s PCI to ISA bridge family The PCI A...

Page 31: ...e user defined threshold The overheat circuitry runs independently from the CPU It can still monitor the overheat condition even if the CPU is in sleep mode Once it detects that the CPU temperature is...

Page 32: ...tection The system BIOS is protected by hardware so that no virus can infect the BIOS area The user can only change the BIOS content through the flash utility provided by SUPERMICRO This feature can p...

Page 33: ...specifications and meets WHQL audio requirements The Solo 1 incorporates a microcontroller an ESFMTM music synthesizer a 3 D stereo effects processor 16 bit stereo wave ADC and DAC 16 bit stereo musi...

Page 34: ...ctures while providing a processor architecture indepen dent implementation that is compatible with both Windows 98 and Windows NT 5 0 Microsoft OnNow The OnNow design initiative is a comprehensive sy...

Page 35: ...ter which is powered off Remote PC setup updates and asset tracking can occur after hours and on weekends so that daily LAN traffic is kept to a minimum and users are not interrupted The motherboards...

Page 36: ...d data transfer rates of 250 Kb s 500 Kb s or 1 Mb s The Super I O provides two high speed serial communication ports UARTs one of which supports serial Infrared communication Each UART includes a 16...

Page 37: ...commodate more devices SUPER P6DBU P6SBU has an on board SCSI controller which is 100 compat ible with all major operating and hardware platforms The AIC 7890 controller provides advanced PCI to SCSI...

Page 38: ...Chapter 1 Introduction 1 29...

Page 39: ...handling chips or modules avoid touching their pins Put the system board and peripherals back into their anti static bags when not in use For grouonding purposes be sure your computer system s chassi...

Page 40: ...the fan heatsink making sure that the hole and clip are on the outside edge of the support If the supports are reversed the holes will not line up with the pegs on the motherboard Slide each support t...

Page 41: ...ard until they click into place to hold the pegs securely Apply slight pressure on the peg and push the peg toward the clip while pushing the clip forward Push the latches on the processor B outward u...

Page 42: ...ard Install the two pins into the base bar Insert the Pentium II with the heat sink on it into Slot 1 Install the top support bar The four top posts should be close to Slot 1 The bottom most row of fi...

Page 43: ...e socket noting that the notches need to line up These directions may not apply to second source URMs 2 4 Special Instructions for the Celeron Processor Please Note The Celeron Processor requires spec...

Page 44: ...Manual Top view of Celeron cap R Tab Note notch in socket Screw holes for retention mechanism Supero L R R L URM with arms folded Note Left and Right arms are defined Figure 2 6 URM and Celeron Insta...

Page 45: ...the CPU speed by the bus speed 100 MHz If you have a 400 MHz CPU dividing it by 100 will give you a CPU Core BUS Ratio of 4 0 After determining the CPU Core Bus Ra tio refer to Table 2 1 for settings...

Page 46: ...r supply Table 2 2 ATX Power Supply Connector Pin Definitions for J32 Pin Number Definition 1 3 3V 2 3 3V3 3 Ground 4 5V 5 Ground 6 5V 7 Ground 8 PW OK 9 5VSB 10 12V Pin Number Definition 11 3 3V 12 1...

Page 47: ...Definition PW_ON Ground Table 2 5 PW ON Connector Pin Definitions for JF2 Table 2 7 Hard Drive LED Pin Definitions for JF1 Pin Number 1 2 3 4 Definition 5V HD Active HD Active 5V Pin Number 12 13 Defi...

Page 48: ...ystem or when the system comes back from AC power failure In this state the power will not come on unless you hit the power switch on the motherboard PIIX4E control is used if you want the system to b...

Page 49: ...e CMOS For ATX power supply you need to com pletely shut down the system then use JBT1 to clear the CMOS Do not use the PW_ON connector to clear the CMOS A second way of resetting the CMOS contents is...

Page 50: ...ng the DIM modules to prevent any possible damages DIM Module Installation 1 Insert DIM modules in Bank 0 through Bank 3 as required for the desired system memory 2 Insert each DIM module vertically i...

Page 51: ...disk drive ribbon cable has 34 wires and two connectors to provide for two floppy disk drives The connector with twisted wires always connects to drive A and the connector that does not have the twist...

Page 52: ...D 24 GND 26 GND 28 BALE 30 GND 32 IOCS16 34 GND 36 Addr 2 38 Chip Select 1 40 GND Table 2 21 IDE Connector Pin Definitions Pin Number Function 1 Strobe 3 Data Bit 0 5 Data Bit 1 7 Data Bit 2 9 Data Bi...

Page 53: ...65 DB 8 66 DB 9 67 DB 10 68 DB 11 Table 2 22 68 pin Single End SCSI Connector Pin Pin Number Function 1 GND 2 GND 3 GND 4 GND 5 GND 6 GND 7 GND 8 GND 9 GND 10 GND 11 GND 12 Reserved 13 Open 14 Reserv...

Page 54: ...O DB 8 DB 9 DB 10 DB 11 Connector Contact Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Signal Names DB 12 DB 13 DB 14 DB 15 DB P1 DB 0 DB 1 DB 2...

Page 55: ...NT VCC3 3 ST1 Reserved PIPE GND Spare SBA1 VCC3 3 SBA3 Reserved GND SBA5 SBA7 KEY KEY KEY KEY AD30 AD28 VCC3 3 AD26 AD24 GND Reserved C BE3 B Vddq3 3 AD21 AD19 GND AD17 C BE2 Vddq3 3 IRDY GND VCC3 3 D...

Page 56: ...cept the video graphics card Be sure the video graphics card is inserted properly 4 Install a CPU the chassis speaker and the power LED to the motherboard Check all the jumper settings as well 5 Insta...

Page 57: ...settings clock speed and voltage settings 4 Use the speaker to determine if any beep codes exist Refer to Appendix A for details about beep codes NOTE If you are a system integrator VAR or OEM a POST...

Page 58: ...ble problem s with the specific system configuration that was sold to you 3 BIOS upgrades can be downloaded from the SUPER BBS 408 895 2022 24 hours a day using 1200 28800 baud 8 data bits 1 stop bit...

Page 59: ...ffered SDRAM cannot be mixed 4 Mixing PC 100 DIMM and PC 66 DIMM will result in an unexpected memory count or system errors 5 User should populate the DIMM starting with the DIMM socket located the fu...

Page 60: ...drive A Press and hold CTRL and Home at the same time then turn on power with these keys pressed until your floppy drive starts reading Your screen will remain blank until the BIOS program is done If...

Page 61: ...ave instant off capabilities as long as the BIOS has control of the system When this feature is disabled or when the BIOS is not in control such as during memory count the first screen that appears wh...

Page 62: ...with the date of purchase is required before any warranty service will be rendered You can obtain service by calling your vendor for a Returned Merchandise Authorization RMA number When returning to...

Page 63: ...place to store system information when the computer is turned off The original IBM AT had 64 bytes of non volatile memory storage in CMOS RAM All AT compatible systems have at least 64 bytes of CMOS...

Page 64: ...AMIBIOS supports the LS120 drive made by Matsushita Kotobuki Electronics Industries Ltd The LS120 can be used as a boot device is accessible as the next available floppy drive AMIBIOS supports PC Hea...

Page 65: ...RQ 10 PCI Onboard SCSI IRQ 10 PCI Slot 4 VGA IRQ 11 AMIBIOS Setup See the following page for examples of the AMIBIOS Setup screen featuring options and settings Figure 4 1 shows the Standard option hi...

Page 66: ...BIOS User s Manual 4 4 Figure 4 1 Standard Option Highlighted Figure 4 2 Settings for Standard Option...

Page 67: ...on Select Auto Detect IDE to let AMIBIOS automatically configure the drive A screen with a list of drive parameters appears Click on OK to configure the drive Type How to Configure SCSI Select Type Se...

Page 68: ...r of cylinders in the disk drive Heads The number of heads Write The size of a sector gets progressively smaller as the track Precompensation diameter diminishes Yet each sector must still hold 512 by...

Page 69: ...est Advanced Setup option The settings are Setting Description Disabled AMIBIOS tests all system memory AMIBIOS waits up to 40 seconds for a READY signal from the IDE hard disk drive AMIBIOS waits for...

Page 70: ...o on For example if the system has a hard disk connected to Primary Slave and another hard disk to Secondary Master then 1st IDE HDD will be referred to as the hard disk connected to Primary Slave and...

Page 71: ...f no add on ROM is found then the current display mode will remain unchanged even if this setup question is selected as Force BIOS If selected as Keep Current then the current display mode will remain...

Page 72: ...settings are No or Yes CPU Microcode Updation Set this option to Enabled to permit the CPU to be updated on line The settings for this option are Enabled or Disabled Internal Cache This option is for...

Page 73: ...ese options enable shadowing of the contents of the ROM area named in the option The ROM area not used by ISA adapter cards is allocated to PCI adapter cards The settings are Disabled Enabled or Cache...

Page 74: ...access outside of AGP aperture and outside of main DRAM range i e in the 640k 1M range or above TOM The 82443BX can assert SERR upon detecting an invalid AGP master access outside of AGP aperture The...

Page 75: ...uses PCI1 and PCI0 Memory Autosizing Support The dynamic detection and sizing of SDRAM and EDO is performed by the BIOS in a system populated with memory which has no SPD information When set to Enabl...

Page 76: ...Refresh signals to DRAM system memory The settings for this option are 15 6 us micro sec onds 31 2 us 62 4 us 124 8 us or 249 6 us Memory Hole This option specifies the location of an area of memory...

Page 77: ...ted clock Graphics Aperture Size This option specifies the amount of system memory that can be used by the Accelerated Graphics Port AGP The settings are 4 MB 8 MB 16 MB 32 MB 64 MB 128 MB or 256 MB S...

Page 78: ...The settings are Disabled 1 SYSCLK 2 SYSCLKs 3 SYSCLKs 4 SYSCLKs 5 SYSCLKs 6 SYSCLKs 7 SYSCLKs or 8 SYSCLKs PIIX4 SERR This signal is asserted to indicate a PIIX4 System Error condition The settings...

Page 79: ...ting only 5 1 4 Power Management Power Management The settings for this feature are APM ACPI or Disabled Set to APM to enable the power conservation feature specified by Intel and Microsoft INT 15h Ad...

Page 80: ...d Hard Disk Timeout Minutes This option specifies the length of a period of hard disk drive inactivity When this length of time expires the computer enters power conserving state specified in the Hard...

Page 81: ...hen set to Monitor these options enable event monitoring on the specified hardware interrupt request line If set to Monitor and the computer is in a power saving state AMIBIOS watches for activity on...

Page 82: ...ten by the CPU is only directed to the PCI VGA device s palette registers If enabled data read and written by the CPU is directed to both the PCI VGA device s palette registers and the ISA VGA palette...

Page 83: ...d Hardwired INTA INTB INTC or INTD PCI Slot1 IRQ Priority PCI Slot2 IRQ Priority PCI Slot3 IRQ Priority PCI Slot4 IRQ Priority These options specify the IRQ priority for PCI devices installed in the P...

Page 84: ...d 16K 32K or 64K Reserved Memory Address This option specifies the beginning address in hex of the reserved memory area The specified ROM memory area is reserved for use by legacy ISA adapter cards Th...

Page 85: ...nitoring The motherboards with W83781D have seven on board voltage monitors for the CPU core CPU I O 3 3V 5V 5V 12V and 12V and three fan status monitors On Board FDC This option enables the FDC Flopp...

Page 86: ...directional transfers Use EPP Enhanced Parallel Port to provide asymmetric bidirectional data transfer driven by the host device Use ECP Extended Capabilities Port to achieve data transfer rates of up...

Page 87: ...each letter via the pen stylus Pen access must be customized for each specific hardware platform When you select Supervisor or User AMIBIOS prompts for a password You must set the Supervisor password...

Page 88: ...4 1 Optimal Default The Optimal default settings provide optimum performance settings for all devices and system features 5 4 2 Fail Safe Default The Fail Safe default settings consist of the safest s...

Page 89: ...on the screen Fatal errors are those which will not allow the system to continue the boot up procedure If a fatal error occurs you should consult with your system manufacturer for possible repairs Th...

Page 90: ...r 6 8042 Gate A20 Failure The keyboard controller 8042 contains the Gate A20 switch which allows the CPU to operate in virtual mode This error means that the BIOS cannot switch the CPU into protected...

Page 91: ...t still beeps replace the keyboard controller If it still beeps try a different keyboard or replace the keyboard fuse if the keyboard has one 8 times there is a memory error on the video adapter Repla...

Page 92: ...Timer Error Most ISA computers include two times There is an error in time 2 CMOS Battery State Low CMOS RAM is powered by a battery The battery power is low Replace the battery CMOS Checksum Failure...

Page 93: ...ollow the screen instructions Display Switch Some compters require a video switch on the Not Proper motherboard be set to either color or monochrome Turn the computer off set the switch then power on...

Page 94: ...No ROM BASIC Cannot find a bootable sector on either disk drive A or hard disk drive C The BIOS calls INT 18h which generates this message Use a bootable disk Off Board Parity error in memory installe...

Page 95: ...bling cache memory 06 Uncompressing the post code unit next 07 Next initializing the CPU init and the CPU data area 08 The CMOS checksum calculation is done next 0B Next performing any required initia...

Page 96: ...14 The 8254 timer test will begin next 19 The 8254 timer test is over Starting the memory refresh test next 1A The memory refresh test line is toggling Checking the 15 second on off time next 23 Read...

Page 97: ...rol to BIOS POST Performing any required processing after the video ROM had control 2E Completed post video ROM test processing If the EGA VGA controller is not found performing the display memory rea...

Page 98: ...next 45 Data initialized Checking for memory wraparound at 0 0 and finding the total system memory size next 46 The memory wraparound test has completed The memory size calculation has been completed...

Page 99: ...Adjusting the displayed memory size for relocation and shadowing next 51 The memory size display was adjusted for relocation and shadowing Testing the memory above 1 MB next 52 The memory above 1 MB h...

Page 100: ...he output buffer and checking for stuck keys Issuing the keyboard reset command next 81 A keyboard reset error or stuck key was found Issuing the keyboard controller interface test command next 82 The...

Page 101: ...mouse check and extended BIOS data area allocation check next 8C Programming the WINBIOS Setup options next 8D The WINBIOS Setup options are programmed Resetting the hard disk controller next 8F The...

Page 102: ...alization after the Coprocessor test next 9E Initialization after the Coprocessor test is complete Checking the extended keyboard keyboard ID and Num Lock key next Issuing the keyboard ID command next...

Page 103: ...B1 Copying any code to specific areas D0h The NMI is disabled Power on delay is starting Next the initialization cade checksum will be verified D1h Initializing the DMA controller Performing the keybo...

Page 104: ...BIOS User s Manual B 10 If either Ctrl Home was pressed or the system BIOS checksum is bad next the system will go to checkpoint code E0h Otherwise going to checkpoint code D7h...

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