BIOS User's Manual
5-8
SERR# (System Error)
The settings for this option are
Enabled
or
Disabled
. Set to
Enabled
to
enable the SERR# signal on the bus. BX asserts this signal to indicate a
system error condition. SERR# is asserted under the following condi-
tions:
- In an ECC configuration, the 82443BX asserts SERR#, for single bit (correctable) ECC errors or multiple
bit (non-correctable) ECC errors if SERR# signaling is enabled via the ERRCMD control register. Any
ECC errors received during initialization should be ignored.
- The 82443BX asserts SERR# for one clock when it detects a target abort during 82443BX initiated PCI
cycle
- The 82443BX can also assert SERR# when a PCI parity error occurs during the address or data phase
- The 82443BX can assert SERR# when it detects a PCI address or data parity error on AGP
- The 82443BX can assert SERR# upon detection of access to an invalid entry in the Graphics Aperature
Translation Table
- The 82443BX can assert SERR# upon detecting an invalid AGP master access outside of AGP aperture
and outside of main DRAM range (i.e. in the 640k - 1M range or above TOM)
- The 82443BX can assert SERR# upon detecting an invalid AGP master access outside of AGP aperture.
- The 82443BX asserts SERR# for one clock when it detects a target abort during 82443BX initiated AGP
cycle
PERR#
This option signals data parity errors of the PCI bus. The settings are
Enabled
or
Disabled
. Set to
Enabled
to enable the PERR# signal.
WSC# Handshake (Write Snoop Complete)
This signal is asserted active to indicate that all the snoop activity on the
CPU bus on the behalf of the last PCI-DRAM write transaction is complete
and that it is safe to send the APIC interrupt message. The settings for
this option are
Enabled
or
Disabled
. Set to
Enabled
to enable hand-
shaking for the WSC# signal.
USWC Write Post
The settings for this option are
Enabled
or
Disabled
. This option sets
the status of USWC (Uncacheable, Speculative, Write-Combining) posted
writes and is used to combine several partial writes to the frame buffer
into a single write in order to reduce the data bus traffic. Set to
Enabled
to enable USWC posted writes to I/O. Set to
Disabled
to disable USWC
posted writes to I/O.
Summary of Contents for SUPER P6DBE
Page 12: ...Chapter 1 Introduction 1 3 Notes...
Page 38: ...Chapter 1 Introduction 1 29...
