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CIRCUIT DESCRIPTION
The DG535 has three printed circuit boards. The
"top" printed circuit board (Figure 8) contains
the unregulated power supplies, microprocessor,
GPIB interface, and the slow counters
(<20MHz) that are used in each of the four time
delays. The "bottom" PCB (Figure 9) contains
the 80MHz PLL reference clock, ECL counters
which are used in each of the four time delays,
jitter compensation circuits, analog delay
circuits, trigger circuits, and the fast rise time
output line drivers. The "front" PCB (Figure 10)
holds the key pad and status LED indicator
lamps. The electroluminescent back lit LCD is
mounted above the "front" PCB. A block
diagram for the DG535 is depicted in Figure 6.
MICROPROCESSOR SYSTEM
The DG535 is controlled by a Z-80B
microprocessor (U303) which is clocked by a
5MHz source which is derived from the 80MHz
PLL clock on the "bottom" PCB. The unit's
firmware resides in a 27128 UVEPROM
(U402). This ROM also contains the calibration
bytes that were determined when the unit was
manufactured. The system uses 8K Bytes of
RAM (U403). While operating, the supply
current to the RAM comes from the +5VDC
supply via D501. When the power is turned off,
a Lithium battery provides power to the RAM
via D502 (to retain the instrument settings) and
RESET is asserted which disables further chip
selects which are normally routed to the RAM
via Q501.
IEEE-488 INTERFACE
The interface to the IEEE-488 is provided by
U302, a TMS9914A GPIB controller. U301 and
U401 are the line receiver/drivers which
interface the controller IC to the IEEE-488 bus.
The data bus driver is configured with open
collector outputs. The controller IC handles all
of the handshaking requirements to the bus, and
interrupts the microprocessor if commands or
data are sent to the instrument.
KEY PAD and LED INDICATORS
The "front" PCB, which holds the key pad and
the status LED's is connected to the "top" PCB
by a 20 pin ribbon cable. The octal latch, U409,
controls the eight status LED's. The eight switch
lines, SWR1-SWR8, are normally held low by
RN701. A key press is detected by scanning the key
pad with the REM, NUM and CURS LED control
lines and reading the switch input port. The diodes
D709, D710, and D711 prevent simultaneous key
presses from shorting out two LED control lines.
LCD DISPLAY
The connector to the front panel LCD, J14, ties
directly to the Z-80's data bus. Besides the eight data
lines on J14, there are two address lines, a chip-
select, a display contrast control, +5VDC and
ground. The 120 VAC required for the back lit
electroluminescent display are wired directly to the
120VAC primary tap on the transformer: use
caution to avoid electric shock.
OUTPUT PORTS ON THE TOP PCB
The Octal Buffer U408, a 74HC244, is used to
buffer the Z-80's data bus to the six octal output
ports and six LSI counter/timer IC's which are on the
"top" PCB, and to the 40 pin connector which goes
to the "bottom" PCB. This data bus buffer is only
active during I/O requests by the Z-80.
Octal Latch
Description
U202
Preset data for HC191's (A&B)
U203
Preset data for HC191's (C&D)
U204
Internal rate generator control
U409
Front panel LED's
U410
Output impedance control
U411
Polarity and trigger control
Each of the six LSI counter/timer IC's (uPD8253)
have three independent 16 bit counter channels.
Three channels are used in each of the four digital
delays, and the rest are used to generate the 1KHz
timer interrupt and to synthesize the clock for the
internal rate generator.
OUTPUT PORTS ON THE BOTTOM PCB
There are two Octal Latches, U806 and U807 (on
the bottom PCB), which are used to preset the ECL
counters in each of the four delay channels. Another
octal latch, U813, controls four 1:8 analog
multiplexers to refresh 30 sample and hold circuits
with the output of the 12-bit D/A converter. These
30 analog voltages are used to control amplitudes
and offsets, analog time delays, external trigger
