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portion of the delay is complete, A_CNT and its
complement are asserted which causes the
differential pair formed by Q305A and Q306A
to switch the current source away from the OTA
and to the capacitor. The OTA is used to
precharge the capacitor to a programmed
voltage: changing the voltage will change the
duration of the analog delay. The current source
is calibrated to charge the capacitor at a rate of
100mV/ns, the same rate coefficient that is used
in the jitter compensation circuit. The
capacitor's voltage is the input to a differential
comparator formed by Q307A and Q308A. The
jitter voltage is applied to the other side of the
comparator. When the capacitor's voltage equals
the jitter compensation voltage, the analog delay
times-out. In this way, the jitter of the trigger
with respect to the internal 80MHz clock is
canceled.
The output of the differential comparator (the
collector of Q308A) is applied to the ECL OR
gate, 1/4 of U303. The non-inverting output of
the OR gate is applied to the ECL exclusive OR
gate which can invert polarity of the output
pulse. The inverting output of the ECL or gate is
wire-ORed with the outputs from the other
channels. The reset cycle is started when this
wire-ORed signal goes low, indicating that all of
the delay channels have timed out. During the
reset cycle, ECL_HOLD is asserted, holding the
outputs of the ECL OR gate high.
RESET CYCLE AND STATUS BITS
An 800ns reset cycle is initiated by TTL_EOD
when all of the delay channels have timed-out.
TTL_EOD clocks the 2/2 of U311 high,
asserting the GATE pulse. About 200ns later,
C301 will be discharged by R302 and P302, and
so the output of 1/6 of U312 will go high,
asserting the LOAD pulse. About 250ns later,
the LOAD pulse is terminated by R304 and
P303 charging C303, which brings the output of
the 2/2 of U312 low. The GATE pulse, and so
the reset cycle, is terminated 350ns later when
C302 is discharged by R303 and P301, resetting
the flip-flop. U311 and U312 are powered from
a se5.0VDC regulator, U313, to prevent
noise from modulating the reset cycle timing.
The reset cycle can be initiated by the Z-80 by
asserting the CPU_RELOAD signal. CPU
reloads are required when the digital delays are
changed, so that the counters will be preset to their
new values. This signal will reset the 1/2 of U311,
presetting the 2/2 of U311 and so start the reset
cycle. The 1/2 of U311 is set immediately by the
GATE-bar signal, enabling the circuit for the next
CPU_RELOAD. Note that the HOLD pulse, which
maintains the BNC outputs in their time-out state
during a normal reset cycle, is disabled during a
CPU initiated reset cycle.
The GATE and LOAD pulses are used throughout
the system to preset the ECL, HC, and LSI counters
and to precharge the capacitors in the analog delays
and jitter compensation circuits.
Three status bits are available to allow the processor
know the state of the delay cycle: BUSY is high if
either TTL_LATCH is high or if a reset cycle is in
progress. TRIGGERED will be high if a BUSY
occurred since the last polling of this bit.
OVERRUN will be set if the unit is triggered while
BUSY with the current timing or reset cycle. Both
TRIGGERED and OVERRUN are reset after they
are polled by the Z-80 asserting the FLAG_CLR bit.
OUTPUT DRIVERS
The output drivers for each output, T0, A, B, C and
D, are essentially the same. Circuit references to
channel A will be used in this description.
The outputs of the exclusive-or gate are shifted and
attenuated by the resistor network N301A, and used
to drive the bases of the output driver transistors
Q309A and Q310A. The common emitter current
source is switched between R321A and the output
BNC by these transistors. The amplitude of the
output pulse is set by the common emitter current
source, Q316A, which is controlled by the D/A
output A_AMP.
OFFSET CONTROL
The DC offset voltage of the outputs is controlled by
the bipolar current source formed by Q302, Q303
and the op-amps 1/4 and 4/4 of U313. This current
source is set by the D/A output, OFFSET_CNTL.
When sourcing current to the output, only Q303 is
on, and the 1/4 of U313 amplifies the differential
voltage across the 10
Ω
shunt resistor, R304A. This
signal is fed-back to the error amplifier, 4/4 of
U313, for comparison to the programmed level,
OFFSET_CNTL. The error amplifier drives the base
