26
Each of the four delay channels behave like a 37
bit presettable synchronous binary ECL counter.
Each channel actually consists of a 2 bit ECL
counter (a 10131 dual flip-flop), a 4 bit HC
counter (a 74HC191), and three 16 bit LSI
counters (uPD8253's). To overcome the long
propagation delays in the HC and LSI counters,
there are two ECL flip-flops that re-synchronize
the counter output to the 80MHz clock.
Throughout the instrument there are many
places where signals must be converted between
ECL and HCMOS levels. To convert from ECL
to HCMOS, a 10125 Quad ECL to TTL
converter is used, with a resistor pull-up. To
convert from HCMOS to ECL, a three-resistor
network is used.
Analog time delay circuits provide delays from
0 to 12.495ns so that delays may be set with a
5ps resolution. These analog delays also
compensate for the jitter in the digital delay
output which arises from the uncertainty in the
phase of an external trigger with respect to the
80MHz internal clock. Without jitter
compensation this uncertainty would give rise to
a 12.5ns jitter.
JITTER COMPENSATION
The purpose of the jitter compensation circuit is
to produce a voltage, which is proportional to
the time between the trigger and a rising edge of
the 80MHz clock. This voltage is used to
modify the analog delays on each channel so as
to eliminate this large component of output
jitter.
The jitter voltage is produced by integrating a
constant current source on a capacitor for the
time that the jitter pulse is present. The constant
current source, Q113, is controlled by a D/A
output from the processor. The D/A voltage,
which is stored on C108, is compared to the
voltage across the resistor R137. The correct
D/A voltage is determined in final calibration of
the instrument and is stored in the unit's ROM.
A very low leakage current switch formed by
Q111 and Q112 is controlled by
JITTER_PULSE. While the jitter pulse is on, all
of the current is drawn from the integrating
capacitor, C106. The voltage on C106 will be
reduced by exactly 100mV per nanosecond of
jitter pulse. The voltage on C106 is buffered by
Q109, a J310 FET, level shifted by D102, a 12V
Zener, to drive the base of the emitter-follower,
Q110. The emitter of Q110 is the source of the jitter
compensation voltage for all of the analog delay
circuits. The JFET and Zener are biased by the
constant current source, Q116, a JFET run at
Id=Idss.
Small leakage currents can cause the jitter voltage to
drift. The dual op-amp, U112, prevents the jitter
voltage from drifting so far as to cause a problem
with the analog delay circuits. If the jitter voltage
drifts up beyond the safe limit, 2/2 of U112 will
lower the drain voltage to Q109 to stop the drift.
(The safe upper limit threshold is reduced during the
timing cycle by the size of the step at the collector
of Q106. In this way, the drift limit circuit is not
active while the timing cycle is not active, allowing
the precharge of the integrating capacitor.) If the
jitter voltage drifts down below -7.4VDC, then 1/2
of U112 will raise the voltage on the source of Q116
and so stop the downward drift.
JITTER PRECHARGE AND S&H
Three reference voltages are generated by the op-
amp, 1/4 of U312. The input to this circuit is the
+10.000VDC reference. The op-amp is configured
with a gain of -1.07 to produce an output of -
10.70VDC. The output is divided to produce
reference levels of -7.40 and -4.00VDC.
The -4.0VDC is the pre-trigger level for the jitter
voltage. Before the trigger, ECL_LATCH is low and
so Q107 is on, and so its collector is about 3Volts
above the -15VDC supply. This will provide about
1mA to the bias input
(pin 16) of the Operational
Transconductance Amplifier, 1/2 U111. The OTA
will source or sink current to the integrating
capacitor to bring the jitter voltage to -4.0VDC.
When the unit is triggered, ECL_LATCH goes high,
turning off the OTA.
The integrating capacitor, C106, needs to be small
so that its voltage may change appreciably during
the brief jitter pulse. However, small leakage
currents will rapidly discharge such a small
capacitor. To eliminate this problem a much larger
capacitor, C104, is charged by an OTA , 2/2 of
U111, to provide a charge reservoir. This sample
and hold OTA is active only during the first few
microseconds after the trigger since the bias current
to the OTA drops off as C103 discharges.
