25
set according to the selection, which is made in
the TRIG Menu. If EXT trigger is selected, then
the output of the rate generator is set to either 0
or 1 in order to control the polarity of the
external trigger. If an INT trigger is selected,
then either the VCO or the divided VCO is
selected as the output to trigger the delay
generator. If a BURst mode is selected, then the
VCO or divided VCO is gated through U310 to
produce a burst of triggers. The number of
pulses in the burst is controlled by 2/3 of U209
and the interval between bursts is controlled by
1/3 of U209. The dual D-type flip-flop, U109, is
used to synchronize the gate to U310 so that the
falling edge of the output triggers is not affected
by the propagation delay through the LSI
counters.
Control Bits
Burst Clk_Sel Int_Trig Output
0
0
0
VCO
0
1
0
VCO/N
0
0
1
Line Trig
0
1
1
0 (Trig on Fall)
1
0
0
Burst VCO
1
1
0
Burst VCO/N
1
0
1
Line Trig
1
1
1
1 (Trig on Rise)
TRIGGER CIRCUITS
The digital delay generator may be triggered
internally or externally. To trigger externally,
the control bit EXT_TRIG is set high (Pin 19,
U411 and Pin 12 on J16), and TRIG_POL is set
high to trigger on rising edges or low to trigger
on falling edges of the external trigger input.
External triggers are discriminated by the fast
Schmitt Trigger which compares the external
trigger to the TRIG_THRES voltage from the
D/A. The input impedance of the EXT TRIG
input is 50
Ω
if R
1
0
1
is shorted to ground by
Q101 which may be turned on by a high level at
TRIG_TERM. The comparator input, Q114, is
protected from excessive inputs by the series
impedance of R104 and R107. The input offset
voltage (due to the difference in Vgs between
Q114 and Q115) is corrected by a calibration
byte in the unit's ROM. The source follower
outputs of the JFETs are applied to the
differential pair Q102 and Q103; the outputs of this
differential pair is applied to the differential pair
formed by Q104 and Q105 which shifts the
comparator's output to ECL levels. A 1K
Ω
resistor
from the collector of Q104 to the source of Q114
provides about 100mV of hysteresis.
The ECL output from the comparator may be
inverted by the exclusive-or gate, 1/2 of U102,
under the control of the TRIG_POLarity bit. If
TRIG_POL=1 then the exclusive-or gate inverts the
comparator's output so that a rising edge at the
trigger input will trigger the unit.
If INTernal trigger is selected from the trigger menu,
then EXT_TRIG will be set low, forcing the output
of the comparator to an ECL low level, and the unit
may be triggered by a falling edge of INT_TRIG.
A Single Shot trigger is done by bringing the
INT_TRIG/TRIG_POL bit low once, while the
EXT_TRIG bit is low. All trigger modes may be
stopped by setting the TRIG_INH bit (Pin 5 of
U411) to a high level.
TRIGGER SEQUENCE
The delay cycle is initiated when the ECL flip-flop,
1/2 U103, is clocked low. The output of this flip-
flop is used to: (1) set TTL_LATCH high so that the
processor can see that a timing cycle is in progress,
(2) commute the current in the differential pair of
Q106 and Q107 to turn off the circuit which
precharges the jitter compensation voltage, (3) start
the leading edge of the "Jitter Pulse" which will
measure the time between the trigger and the rising
edge of 80MHz clock, and (4) start a "1" shifting
through the two-bit shift register formed by U105.
The two-bit shift register provides an output which
is synchronous with the rising edge of the 80MHz
clock. This output is used to terminate the jitter
pulse and to enable the five or-gates which
multiplex the 80MHz clock to the ECL counters for
channels T0, A, B, C, and D.
OVERVIEW OF THE DELAY CHANNELS
The basic time interval in the digital delay generator
is the 80MHz clock, which has a period of 12.5ns.
Time intervals from 0 to 1000s require that each
channel be able to count from 0 to 80,000,000,000
cycles of the clock. The high count rate requires
using ECL, however, the large number of counts
precludes using ECL exclusively.
