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RUPI/80C186 Interface
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Provides bridge between CPU and mainframe SDLC
communications bus.
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SDLC runs asynchronous of the CPU in communicating with the
mainframe.
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RUPI/CPU Bus Interface circuit consists of an 8-bit wide
transceiver connected to Port 0 of the RUPI, and general logic.
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RUPI informs the CPU of the current transfer direction via the
XMIT or RECV lines.
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XMIT tells the CPU that the RUPI is receiving data from the
monitor and is transmitting it to the CPU.
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RECV indicates the RUPI is sending data to the monitor and is
receiving it from the CPU.
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448 Hz interrupt defines the frame time of the CPU and the
front-end data rate of the system.
ECG Data Interface
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ECG data from the digital PCBA is input to the CPU PCBA at J2
via the power supply PCBA.
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Gating of the counter and generation of DRQ1 is accomplished
by the pulse width and control bus PAL, implemented in a
programmable logic device (EPLD).
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CPU reads this count eight times during each 2.2-msec frame
time, as determined by the 448 Hz interrupt.
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448 Hz control pulse selects leads and synchronizes the ECG/
respiration PCBA multiplexer.
High-Level Outputs and Defibrillator Sync Input
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The high-level output (HLO) is provided at a 0.177-inch phone
jack on the module front panel.
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The 90478 HLO is the primary analog output for an ECG
waveform, low-pass filtered at 130 Hz:
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Has multi-purpose I/O stereo jack.
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Provides ECG output on the tip connection, defibrillator sync
input on the ring connection, and a reference ground on the
sleeve.
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DEFIB sync input is routed to a DEFIB debounce circuit and
input to the CPU via the EPLD.
