Sony LMT-300, Service Manual

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4-2 (E)
LMT-300
4-4. PU-131 Board
The PU-131 board mounts two functional blocks, that is, an SMS block which realizes an SMS function
that controls the whole projection system and a media block controller which controls the ingestion or
reproduction of DCP.
4-4-1. SMS Block
An SMSCPU board is mounted in CN101 on the PU-131 board and connected with peripheral devices
from various interfaces of PCI/VGA/USB/Gigabit Ethernet, LPC, and SATA. Gigabit Ethernet devices
(IC205 and IC305) are connected to a PCI signal and then connected to the CTRL IN terminal (CN201)
and PRJ CTRL terminal (CN301) on the rear panel. A VGA signal is directly connected to the VGA termi-
nal (CN3502) on the rear panel, and a USB1-4 signal is directly connected to the INGEST PORT/TPC
terminal (CN401) and SPARE1/SPARE2 terminal (CN402) on the rear panel. A USB5-6 signal is con-
nected to the CP-406 board through the MB-1143 board, and a SATA signal is connected to the SSD
assembly through the MB-1143 board. An LPC signal is converted into an I
2
C signal using FPGA
(IC1602) and connected to PLD on the CP-406 and IO-243 boards so as to receive and send a GPIO
signal. SMS and media blocks controller are connected through IC3501 on the PU-131 board using a
Gigabit Ethernet signal and used for inter-block communication, control, and DCP ingestion.
4-4-2. Media Block Controller
An MPU-148 board is mounted in CN1001 on the PU-131 board and connected with peripheral devices
using a CPU local bus or PCI-X bus.
A DATA IN terminal (CN3001) is connected to the MPU-148 board through IC3001 on the PU-131 board.
FPGA (IC4501) on the PU-131 board has a data striping function to HDD, an ECC addition/correction
function, an HDD rebuild function, a recording/playback data buffering function using SO-DIMM, and a
data transfer function to the SSP-27/27A board so as to realize the matrix DMA transfer between PCI-X,
SATA, SO-DIMM, and LVDSIF circuits. This media block is connected from SAS1064 (IC7001 and
IC7501), connected to PCI-X of FPGA, to the HDD unit so as to record and reproduce a DCP contents
material group to and from HDD. CPU MISC FPGA (IC1602) has a function for performing the I
2
C bus
control on and out of a board, performing the LED control on the MB-1143 or DP-455 board, and moni-
toring the status of a power unit. Moreover, this block mounts NVRAM (IC2008 to IC2011) that stores
various parameters or logs of HDD using a backup battery (BATT1), a DC-DC converter circuit (consist-
ing of IC2301, IC2400, and IC2101) that generates various voltages from a voltage of
+
12 V supplied to
the PU-131 board, and an ISPPAC circuit (IC1503) that monitors each voltage.
n
Never pull out the PU-131 board because there is a circuit that stores data using a battery.