S i M 3 L 1 x x
36
Rev 1.1
4.1.5.2. Power Mode 1 and Power Mode 5
Power Mode 1 and Power Mode 5 are fully operational modes with code executing from RAM. PM5 is the same as
PM1, but with the clocks operating at a lower speed. This enables power to be conserved by reducing the LDO
regulator outputs. Compared with the corresponding flash operational mode (Normal or PM4), the active power
consumption of the device in these modes is reduced. Additionally, at higher speeds in PM1, the core throughput
can also be increased because RAMdoesnot require additional wait states that reduce the instruction fetch speed.
4.1.5.3. Power Mode 2 and Power Mode 6
In Power Mode 2 and Power Mode 6, the core halts and the peripherals continue to run at the selected clock
speed. PM6 is the same as PM2, but with the clocks operating at a lower speed. This enables power to be
conserved by reducing the LDO regulator outputs. To place the device in PM2 or PM6, the core should execute a
wait-for-interrupt (WFI) or wait-for-event (WFE) instruction. If the WFI instruction is called from an interrupt service
routine, the interrupt that wakes the device from PM2 or PM6 must be of a sufficient priority to be recognized by the
core. It is recommended to perform both a DSB (Data Synchronization Barrier) and an ISB (Instruction
Syncronization Barrier) operation prior to the WFI to ensure all bus accesses complete. When operating from the
LFOSC0, PM6 can achieve similar power consumption to PM3, but with faster wake times and the ability to wake
on any interrupt.
4.1.5.4. Power Mode 3
In Power Mode 3 the core and peripheral clocks are halted. The available sources to wake from PM3 are controlled
by the Power Management Unit (PMU). A special Fast Wake option allows the core to wake faster by keeping the
LFOSC0 or RTC0 clock active. Because the current consumption of these blocks is minimal, it is recommended to
use the fast wake option.
Before entering PM3, the DMA controller should be disabled, and the desired wake source(s) should be configured
in the PMU. The SLEEPDEEP bit in the ARM System Control Register should be set, and the PMSEL bit in the
CLKCTRL0_CONFIG register should be cleared to indicate that PM3 is the desired power mode. For fast wake,
the core clocks (AHB and APB) should be configured to run from the LPOSC, and the PM3 Fast wake option and
clock source should be selected in the PM3CN register.
The device will enter PM3 on a WFI or WFE instruction. If the WFI instruction is called from an interrupt service
routine, the interrupt that wakes the device from PM3 must be of a sufficient priority to be recognized by the core. It
is recommended to perform both a DSB (Data Synchronization Barrier) and an ISB (Instruction Synchronization
Barrier) operation prior to the WFI to ensure all bus access is complete.
4.1.5.5. Power Mode 8
In Power Mode 8, the core and most peripherals are completely powered down, but all registers and selected RAM
blocks retain their state. The LDO regulators are disabled, so all active circuitry operates directly from VBAT.
Alternatively, the PMU has a specialized VBAT-divided-by-2 charge pump that can power some internal modules
while in PM8 to save power. The fully operational functions in this mode are: LPTIMER0 , RTC0, UART0 running
from RTC0TCLK, PMU Pin Wake, the advanced capture counter, and the LCD controller.
This mode provides the lowest power consumption for the device, but requires an appropriate wake up source or
reset to exit. The available wake up or reset sources to wake from PM8 are controlled by the Power Management
Unit (PMU). The available wake up sources are: Low Power Timer (LPTIMER0), RTC0 (alarms and oscillator
failure notification), Comparator 0 (CMP0), advanced capture counter (ACCTR0), LCD VBAT monitor (LCD0),
UART0, low power mode charge pump failure, and PMU Pin Wake. The available reset sources are: RESET pin,
VBAT supply monitor, Comparator 0, Comparator 1, low power mode charge pump failure, RTC0 oscillator failure,
or a PMU wake event.
Before entering PM8, the desired wake source(s) should be configured in the PMU. The SLEEPDEEP bit in the
ARM System Control Register should be set, and the PMSEL bit in the CLKCTRL0_CONFIG register should be set
to indicate that PM8 is the desired power mode.
The device will enter PM8 on a WFI or WFE instruction, and remain in PM8 until a reset configured by the PMU
occurs. It is recommended to perform both a DSB (Data Synchronization Barrier) and an ISB (Instruction
Synchronization Barrier) operation prior to the WFI to ensure all bus access is complete.
Summary of Contents for SiM3L1xx
Page 2: ...2 Rev 1 1 ...
Page 62: ...SiM3L1xx 62 Rev 1 1 6 2 SiM3L1x6 Pin Definitions Figure 6 2 SiM3L1x6 GQ Pinout ...
Page 63: ...SiM3L1xx Rev 1 1 63 Figure 6 3 SiM3L1x6 GM Pinout ...
Page 69: ...SiM3L1xx Rev 1 1 69 6 3 SiM3L1x4 Pin Definitions Figure 6 4 SiM3L1x4 GM Pinout ...
Page 74: ...SiM3L1xx 74 Rev 1 1 6 4 TQFP 80 Package Specifications Figure 6 5 TQFP 80 Package Drawing ...
Page 81: ...SiM3L1xx Rev 1 1 81 6 6 TQFP 64 Package Specifications Figure 6 9 TQFP 64 Package Drawing ...
Page 89: ...SiM3L1xx Rev 1 1 89 Figure 7 3 SiM3L1x4 GM Revision Information ...
