Silicon Laboratories SiM3L1xx, User Manual

Page: 15 / 91

Table 3.3. Power Mode Wake Up Times
Parameter Symbol Test Condition Min Typ Max Unit
Power Mode 2 or 6 Wake Time t
PM2
4 — 5 clocks
Power Mode 3 Fast Wake Time
(using LFO as clock source) t
PM3FW
— 425 — μ s
Power Mode 8 Wake Time t
PM8
— 3.8 — μ s
Notes:
1.
Wake times are specified as the time from the wake source to the execution phase of the first instruction following WFI.
This includes latency to recognize the wake event and fetch the first instruction (assuming wait states = 0).
Table 3.4. Reset and Supply Monitor
Parameter Symbol Test Condition Min Typ Max Unit
V
BAT
High Supply Monitor Threshold
(VBATHITHEN = 1)
V
VBATMH
Early Warning — 2.20 — V
Reset 1.95 2.05 2.1 V
V
BAT
Low Supply Monitor Threshold
(VBATHITHEN = 0)
V
VBATML
Early Warning — 1.85 — V
Reset 1.70 1.75 1.77 V
Power-On Reset (POR) Threshold V
POR
Rising Voltage on
V
BAT
— 1.4 — V
Falling Voltage on
V
BAT
0.8 1 1.3 V
V
BAT
Ramp Time t
RMP
Time to V
BAT
> 1.8 V 10 — 3000 μ s
Reset Delay from POR t
POR
Relative to V
BAT
>
V
POR
3 — 100 ms
Reset Delay from non-POR source t
RST
Time between release
of reset source and
code execution
— 10 — μ s
RESET Low Time to Generate Reset t
RSTL
50 — — ns
Missing Clock Detector Response
Time (final rising edge to reset) t
MCD
F
AHB
> 1 MHz — 0.5 1.5 ms
Missing Clock Detector Trigger
Frequency F
MCD
— 2.5 10 kHz
V
BAT
Supply Monitor Turn-On Time t
MON
— 2 — μ s
S i M 3 L 1 x x
Rev 1.1 15