Silicon Laboratories SiM3L1xx, User Manual

Page: 21 / 91

S i M 3 L 1 x x
Rev 1.1 21
Table 3.9. SAR ADC
Parameter Symbol Test Condition Min Typ Max Unit
Resolution N
bits
12 Bit Mode 12 Bits
10 Bit Mode 10 Bits
Supply Voltage Requirements
(VBAT) V
ADC
High Speed Mode 2.2 — 3.8 V
Low Power Mode 1.8 — 3.8 V
Throughput Rate
(High Speed Mode) f
S
12 Bit Mode — — 250 ksps
10 Bit Mode — — 1 Msps
Throughput Rate
(Low Power Mode) f
S
12 Bit Mode — — 62.5 ksps
10 Bit Mode — — 250 ksps
Tracking Time t
TRK
High Speed Mode 230 — — ns
Low Power Mode 450 — — ns
SAR Clock Frequency f
SAR
High Speed Mode — — 16.24 MHz
Low Power Mode — — 4 MHz
Conversion Time t
CNV
10-Bit Conversion,
SAR Clock = 16 MHz,
APB Clock = 40 MHz
762.5 ns
Sample/Hold Capacitor C
SAR
Gain = 1 — 5 — pF
Gain = 0.5 — 2.5 — pF
Input Pin Capacitance C
IN
High Quality Inputs — 18 — pF
Normal Inputs — 20 — pF
Input Mux Impedance R
MUX
High Quality Inputs — 300 —

Normal Inputs — 550 —

Voltage Reference Range V
REF
1 — V
BAT
V
Input Voltage Range* V
IN
Gain = 1 0 — V
REF
V
Gain = 0.5 0 — 2xV
REF
V
Power Supply Rejection Ratio PSRR
ADC
— 70 — dB
DC Performance
Integral Nonlinearity INL 12 Bit Mode — ±1 ±1.9 LSB
10 Bit Mode — ±0.2 ±0.5 LSB
Differential Nonlinearity
(Guaranteed Monotonic) DNL 12 Bit Mode –1 ±0.7 1.8 LSB
10 Bit Mode — ±0.2 ±0.5 LSB
Offset Error (using VREFGND) E
OFF
12 Bit Mode, VREF = 2.4 V –2 0 2 LSB
10 Bit Mode, VREF = 2.4 V –1 0 1 LSB