Silicon Laboratories SiM3L1xx, User Manual

Page: 35 / 91

S i M 3 L 1 x x
Rev 1.1 35

Supports synchronizing the regulator switching with the system clock.

Automatically limits the peak inductor current if the load current rises beyond a safe limit.

Automatically goes into bypass mode if the battery voltage cannot provide sufficient headroom.

Sources current, but cannot sink current.
4.1.2. Three Low Dropout LDO Regulators (LDO0)
The SiM3L1xx devices include one LDO0 module with three low dropout regulators. Each of these regulators have
independent switches to select the battery voltage or the output of the dc-dc converter as the input to each LDO,
and an adjustable output voltage.
The LDOs consume little power and provide flexibility in choosing a power supply for the system. Each regulator
can be independently adjusted between 0.8 and 1.9
V output.
4.1.3. Voltage Supply Monitor (VMON0)
The SiM3L1xx devices include a voltage supply monitor that can monitor the main supply voltage. This module
includes the following features:

Main supply “VBAT Low” (VBAT below the early warning threshold) notification.

Holds the device in reset if the main VBAT supply drops below the VBAT Reset threshold.
The voltage supply monitor allows devices to function in known, safe operating conditions without the need for
external hardware.
4.1.4. Power Management Unit (PMU)
The Power Management Unit on the SiM3L1xx manages the power systems of the device. It manages the power-
up sequence during power on and the wake up sources for PM8. On power-up, the PMU ensures the core voltages
are a proper value before core instruction execution begins.
The VDRV pin powers external circuitry from either the VBAT battery input voltage or the output of the dc-dc
converter on VDC. The PMU includes an internal switch to select one of these sources for the VDRV pin.
The PMU has a specialized VBAT-divided-by-2 charge pump that can power some internal modules while in PM8
to save power.
The PMU module includes the following features:

Provides the enable or disable for the analog power system, including the three LDO regulators.

Up to 14 pin wake inputs can wake the device from Power Mode 8.

The Low Power Timer, RTC0 (alarms and oscillator failure), Comparator 0, Advanced Capture Counter,
LCD0 VBAT monitor, UART0, low power mode charge pump failure, and the RESET pin can also serve as
wake sources for Power Mode 8.

Controls which 4 kB RAM blocks are retained while in Power Mode 8.

Provides a PMU_Asleep signal to a pin as an indicator that the device is in PM8.

Specialized charge pump to reduce power consumption in PM8.
Provides control for the internal switch between VBAT and VDC to power the VDRV pin for external circuitry.
4.1.5. Device Power Modes
The SiM3L1xx devices feature seven low power modes in addition to normal operating mode. Several peripherals
provide wake up sources for these low power modes, including the Low Power Timer (LPTIMER0), RTC0 (alarms
and oscillator failure notification), Comparator 0 (CMP0), Advanced Capture Counter (ACCTR0), LCD VBAT
monitor (LCD0), UART0, low power mode charge pump failure, and PMU Pin Wake.
In addition, all peripherals can have their clocks disabled to reduce power consumption whenever a peripheral is
not being used using the clock control (CLKCTRL) registers.
4.1.5.1. Normal Mode (Power Mode 0) and Power Mode 4
Normal Mode and Power Mode 4 are fully operational modes with code executing from flash memory. PM4 is the
same as Normal Mode, but with the clocks operating at a lower speed. This enables power to be conserved by
reducing the LDO regulator outputs.