S i M 3 L 1 x x
Rev 1.1
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4.5. Data Peripherals
4.5.1. 10-Channel DMA Controller
The DMA facilitates autonomous peripheral operation, allowing the core to finish tasks more quickly without
spending time polling or waiting for peripherals to interrupt. This helps reduce the overall power consumption of the
system, as the device can spend more time in low-power modes.
The DMA controller has the following features:
Utilizes ARM PrimeCell uDMA architecture.
Implements 10 channels.
DMA crossbar supports DTM0, DTM1, DTM2, SARADC0, IDAC0, I2C0, SPI0, SPI1, USART0, AES0,
ENCDEC0, EPCA0, external pin triggers, and timers.
Supports primary, alternate, and scatter-gather data structures to implement various types of transfers.
Access allowed to all AHB and APB memory space.
4.5.2. Data Transfer Managers (DTM0, DTM1, DTM2)
The Data Transfer Manager is a module that collects DMA request signals from various peripherals and generates
a series of master DMA requests based on a state-driven configuration. This master request drives a set of DMA
channels to perform functions such as assembling and transferring communication packets to external devices.
This capability saves power by allowing the core to remain in a low power mode during complex transfer
operations. A combination of simple and peripheral scatter-gather DMA configurations can be used to perform
complex operations while reducing memory requirements.
The DTM acts as a side channel for the peripheral’s DMA control signals. When active, it manages the DMA
control signals for the peripherals. When the DTMn module is inactive, the peripherals communicate directly to the
DMA module.
The DTMn module has the following features:
State descriptions stored in RAM with up to 15 states supported per module.
Supports up to 15 source peripherals and up to 15 destination peripherals per module, in addition to
memory or peripherals that do not require a data request.
Includes error detection and an optional transfer timeout.
Includes notifications for state transitions.
4.5.3. 128/192/256-bit Hardware AES Encryption (AES0)
The basic AES block cipher is implemented in hardware. The integrated hardware support for Cipher Block
Chaining (CBC) and Counter (CTR) algorithms results in identical performance, memory bandwidth, and memory
footprint between the most basic Electronic Codebook (ECB) algorithm and these more complex algorithms. This
hardware accelerator translates to more core bandwidth available for other functions or a power savings for low-
power applications.
The AES module includes the following features:
Operates on 4-word (16-byte) blocks.
Supports key sizes of 128, 192, and 256 bits for both encryption and decryption.
Generates the round key for decryption operations.
All cipher operations can be performed without any firmware intervention for multiple 4-word blocks (up to
32
kB).
Support for various chained and stream-ciphering configurations with XOR paths on both the input and
output.
Internal 4-word FIFOs to facilitate DMA operations.
Integrated key storage.
Hardware acceleration for Electronic Codebook (ECB), Cipher-Block Chaining (CBC), and Counter (CTR)
algorithms utilizing integrated counterblock generation and previous-block caching.
Summary of Contents for SiM3L1xx
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