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OOF

Reference

Hysteresis

OOF Declared

OOF Cleared

-6 ppm

(Set)

-4 ppm

(Clear)

0 ppm

+4 ppm

(Clear)

+6 ppm

(Set)

Figure 5.10. Example of Precise OOF Monitor Assertion and De-assertion Triggers

The table below lists the OOF monitoring and control registers. Because the precision OOF monitor needs to provide 1/16 ppm of fre-

quency measurement accuracy, it must measure the monitored input clock frequencies over a relatively long period of time. This may

be too slow to detect an input clock that is quickly ramping in frequency. An additional level of OOF monitoring called the Fast OOF

monitor runs in parallel with the precision OOF monitors to quickly detect a ramping input frequency. The Fast OOF responds more

quickly and has larger thresholds.

Table 5.9. Out-of-Frequency Status Monitoring and Control Registers

Setting Name

Hex Address [Bit Field]

Function

Si5397

Si5396

OOF Status Indicators

OOF(3,2,1,0)

000D[7:4]

OOF status monitor for IN3, IN2, IN1, IN0. Indicates if a

valid clock is detected or if a OOF condition is detected.

OOF(3,2,1,0)_FLG

0012[7:4]

OOF status monitor sticky bits for IN3, IN2, IN1, IN0.

Sticky bits will remain asserted when an OOF event oc-

curs until cleared. Writing a zero to a sticky bit will clear

it.

OOF(3,2,1,0)_INTR_MSK

0x0018[7:4]

Marks OOF from generating INTRb interrupt for IN3-IN0.

0: Allow OOF interrupt (default)

1: Mask (ignore) OOF for interrupt

OOF Monitor Control and Settings

OOF_REF_SEL

0040[2:0]

This selects the clock that the OOF monitors use as

their “0 ppm” reference. Selections are: XA/XB, IN0,

IN1, IN2, IN3.

OOF(3,2,1,0)_EN

003F[3:0]

This allows to enable/disable the precision OOF monitor

for IN3, IN2, IN1, IN0.

FAST_OOF(3,2,1,0)_EN

003F[7:4]

To enable/disable the fast OOF monitor for IN3, IN2,

IN1, IN0.

OOF(3,2,1,0)_SET_THR

0046[7:0] -

0049[7:0]

0046[7:0] -

0049[7:0]

Determines the OOF alarm set threshold for IN3, IN2,

IN1, IN0. Range is from ±2 ppm to ±500 ppm in steps of

2 ppm.

OOF(3,2,1,0)_CLR_THR

004A[7:0] -

004D[7:0]

004A[7:0] -

004D[7:0]

Determines the OOF alarm clear threshold for INx.

Range is from ±2 ppm to ±500 ppm in steps of 2 ppm.

FAST_OOF(3,2,1,0)_SET_THR

0x0051[7:0] -

0x0054[7:0]

0x0051[7:0] -

0x0054[7:0]

Determines the fast OOF alarm set threshold for IN3,

IN2, IN1, IN0.

FAST_OOF(3,2,1,0)_

CLR_THR

0x0055 [7:0] -

0x0058[7:0]

0x0055 [7:0] -

0x0058[7:0]

Determines the fast OOF alarm clear threshold for IN3,

IN2, IN1, IN0.

Si5397/96 Reference Manual

Clock Inputs

silabs.com

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Rev. 0.9 | 32

Summary of Contents for Si5396 Series

Page 1: ... with superior jitter perform ance Each DSPLL supports independent free run holdover modes of operation and offers automatic and hitless input clock switching The Si5397 96 is programmable via a serial interface with in circuit pro grammable non volatile memory so that it always powers up with a known configuration Programming the Si5397 96 is made easy with Silicon Labs ClockBuilder Pro software ...

Page 2: ...22 5 2 1 Unused Inputs 24 5 2 2 Hitless Input Switching with Phase Buildout 25 5 2 3 Ramped Input Switching 26 5 2 4 Hitless Switching LOL Loss of Lock and Fastlock 26 5 2 5 External Clock Switching 26 5 2 6 Synchronizing to Gapped Input Clocks 27 5 2 7 Rise Time Considerations 28 5 3 Fault Monitoring 29 5 3 1 Input Loss of Signal LOS Fault Detection 30 5 3 2 Out of Frequency OOF Fault Detection 3...

Page 3: ...6 57 9 Serial Interface 59 9 1 I2C Interface 61 9 2 SPI Interface 63 10 XAXB References 68 10 1 External References 68 10 2 Recommended Crystals and Oscillators 68 10 3 Register Settings to Configure for External XTAL Reference 69 10 3 1 XAXB_EXTCLK_EN Reference Clock Selection Register 69 10 3 2 PXAXB Pre scale Divide Ratio for Reference Clock Register 69 11 Internal Reference 70 12 Crystal XO an...

Page 4: ... 15 10 Page A Registers Si5397A B 171 15 11 Page B Registers Si5397A B 172 15 12 Page C Registers Si5397A B 175 16 Si5397C D Register Map 177 16 1 Page 0 Registers Si5397C D 177 16 2 Page 1 Registers Si5397C D 197 16 3 Page 2 Registers Si5397C D 201 16 4 Page 3 Registers Si5397C D 212 16 5 Page 4 Registers Si5397C D 214 16 6 Page 5 Registers Si5397C D 224 16 7 Page 6 Registers Si5397C D 234 16 8 P...

Page 5: ... Page 5 Registers Si5396 301 17 7 Page 9 Registers Si5396 311 17 8 Page A Registers Si5396 312 17 9 Page B Registers Si5396 313 17 10 Page C Registers Si5396 315 18 Revision History 316 silabs com Building a more connected world Rev 0 9 5 ...

Page 6: ...etails from the user to allow focus on the high level input and output configuration making it intuitive to understand and configure for the end application The software walks the user through each step with explanations about each configuration step in the process to explain the different options available The software will restrict the user from entering an invalid combination of selections The ...

Page 7: ...arison Part Number Internal External Reference Number of Inputs Number of Multi Synths Number of Outputs Package Type Si5397A B External 4 4 8 64 QFN Si5397J K Internal 4 4 8 64 LGA Si5397C D External 4 4 4 64 QFN Si5397L M Internal 4 4 4 64 LGA Si5396A B External 4 2 4 44 QFN Si5396J K Internal 4 2 4 44 LGA Si5397 96 Reference Manual Family Product Comparison silabs com Building a more connected ...

Page 8: ...lly using an internal state ma chine The oscillator circuit OSC provides a frequency reference which determines output frequency stability and accuracy while the device is in free run or holdover mode Note that a XTAL or suitable XO reference on XA XB is always required and is the jitter refer ence for the device The high performance MultiSynth dividers Nxn Nxd generate integer or fractionally rel...

Page 9: ...n value is 1 Max value is 224 Fractional M divisors must be 10 56 bit numerator 32 bit denominator Practical M divider range of Fdco 2 MHz M Fdco 8 kHz Each M divider has a separate update bit for the new divider value to take effect Soft reset will also update M divider values 4 Output N dividers N0 N3 0x0302 0x032D MultiSynth divider Integer or fractional divide values 44 bit numerator 32 bit de...

Page 10: ...ase noise jitter it is recommended that the normal PLL bandwidth be kept less than fpfd 160 although ratios of fpfd 100 will typically work fine Note After changing the bandwidth parameters the appropriate BW_UPDATE_PLLx bit 0x414 0x514 0x614 0x714 must be set high to latch the new values into operation The update bits will latch both nominal and fastlock bandwidths Table 3 1 PLL Bandwidth Registe...

Page 11: ... Function Si5397 Si5396 FASTLOCK_AUTO_EN_PLLA 042B 0 042B 0 Fastlock enable disable Fastlock is enabled by default with a bandwidth of 4 kHz FASTLOCK_AUTO_EN_PLLB 052B 0 052B 0 FASTLOCK_AUTO_EN_PLLC 062B 0 FASTLOCK_AUTO_EN_PLLD 072C 0 FAST_BW_PLLA 040E 7 0 0413 7 0 040E 7 0 0413 7 0 Fastlock bandwidth is selectable in the range of 100 Hz up to 4 kHz Register values determined using Clock BuilderPr...

Page 12: ...ut clocks selected Lock Acquisition Fast Lock Locked Mode Holdover Mode Phase lock on selected input clock is achieved An input is qualified and available for selection No valid input clocks available for selection Free run Valid input clock selected Reset and Initialization Power Up Selected input clock fails Yes No Holdover History Valid Other Valid Clock Inputs Available No Yes Input Clock Swit...

Page 13: ...e same function as power cycling the de vice All registers will be restored to their default val ues SOFT_RST_ALL 001C 0 001C 0 Resets the device without re downloading the regis ter configuration from NVM SOFT_RST_PLLA 001C 1 001C 1 Performs a soft reset on DSPLL A only SOFT_RST_PLLB 001C 2 001C 2 Performs a soft reset on DSPLL B only SOFT_RST_PLLC 001C 3 Performs a soft reset on DSPLL C only SOF...

Page 14: ...ng registers require this special sequence of writes Control Register s PXAXB 0x0206 1 0 MXAXB_NUM 0x0235 0x023A MXAXB_DEN 0x023B 0x023E PLL lockup can easily be avoided by using the following the preamble and postamble write sequence below when one of these regis ters is modified or large frequency steps are made Clockbuilder Pro software adds these writes to the output file by default when Ex po...

Page 15: ...re writing registers to NVM 2 You may write to the user scratch space Registers 0x026B to 0x0272 DESIGN_ID0 DESIGN_ID7 to identify the contents of the NVM bank 3 Write 0xC7 to NVM_WRITE register 4 Poll DEVICE_READY until DEVICE_READY 0x0F 5 Set NVM_READ_BANK 0x00E4 0 1 This will load the NVM contents into non volatile memory 6 Poll DEVICE_READY until DEVICE_READY 0x0F 7 Read ACTIVE_NVM_BANK and ve...

Page 16: ... there is little or no jitter attenuation from the XAXB pins to the clock outputs a low jitter XAXB source will be needed for low jitter clock outputs 4 5 Lock Acquisition Mode Each of the DSPLLs independently monitors its configured inputs for a valid clock If at least one valid clock is available for synchroni zation a DSPLL will automatically start the lock acquisition process If the fast lock ...

Page 17: ...quency difference between the output frequency while in holdover and the desired new output frequency is measured It is likely that the new output clock frequency will not be the same as the holdover output frequency because the new input clock frequency might have changed and the XTAL drift might have changed the output frequency The ramp logic calculates the difference in frequency between the h...

Page 18: ...historical average frequency used in Holdover mode Window Length in seconds s Window Length 2LEN 1 268nsec HOLD_HIST_LEN_PLLB 052E 4 0 052E 4 0 HOLD_HIST_LEN_PLLC 062E 4 0 HOLD_HIST_LEN_PLLD 072F 4 0 HOLD_HIST_DELAY_PLLA 042F 4 0 042F 4 0 Delay Time to ignore data for historical average frequen cy in Holdover mode Delay Time in seconds s Delay Time 2DELAY x268nsec HOLD_HIST_DELAY_PLLB 052F 4 0 052...

Page 19: ...396 HOLD_RAMP_EN_PLLA 042C 3 042C 3 Must be set to 1 for normal operation HOLD_RAMP_EN_PLLB 052C 3 052C 3 HOLD_RAMP_EN_PLLC 062C 3 HOLD_RAMP_EN_PLLD 072D 3 Si5397 96 Reference Manual Modes of Operation silabs com Building a more connected world Rev 0 9 19 ...

Page 20: ... or singled ended such as LVCMOS In addition the inputs also accept DC coupled CMOS type inputs with 50 or very low input duty cycle Input selection can be manual pin or register controlled or automatic with user definable priorities There is a register to select pin or register control and to configure the input as shown below Table 5 1 Manual or Automatic Input Clock Selection Control Registers ...

Page 21: ...priority becomes valid then an automatic switch over to that input will be initiated With Non revertive switching the active input will always remain selected while it is valid If it becomes invalid an automatic switchover to the highest priority valid input will be initiated Table 5 3 Automatic Input Select Control Registers Setting Name Hex Address Function Si5397 Si5396 IN 3 2 1 0 _PRIORITY_PLL...

Page 22: ...OS and Non Standard Pulsed CMOS inputs which are all dc coupled inputs 50 100 INx INxb 50 Standard AC Coupled Differential LVDS LVPECL CML Standard AC Coupled Single Ended INx 3 3V 2 5V 1 8V LVCMOS R1 R2 50 RS RS matches the CMOS driver to a 50 ohm transmission line if used C1 INxb This cap should have less than 20 ohms of capacitive reactance at the clock input frequency Only when 3 3V LVCMOS dri...

Page 23: ...dard CMOS R1 R2 50 RS RS matches the CMOS driver to a 50 ohm transmission line if used INxb Clock IC Non Standard Or Pulsed CMOS Clock IC Attenuation circuit not required for 1 8V input or if all input specifications in datasheet are met Attenuation circuit recommended but not required if input specifications in datasheet are met Figure 5 3 Input Terminations for DC Coupled Standard CMOS and Non S...

Page 24: ...or standard mode inputs both input pins must be properly connected as shown in the above figure including the Standard AC Coupled Single Ended case In any of the CMOS modes it is not necessary to connect the inverting INx input pin To place the input buffer into any one of the CMOS modes the corresponding bit must be set in IN_PULSED_CMOS_EN 0x0949 7 4 Make sure the corresponding input bit is set ...

Page 25: ...bandwidth Lower PLL loop bandwidth provides more filtering Hitless Switching with Phase Buildout should be used for applications where the input clocks are all locked to a common upstream clock as in most synchronization systems Hitless switching is supported for input frequencies down to 8 kHz Gapped clocks are not recommended for use with Hitless Switching as this may increase the phase transien...

Page 26: ...from Holdover Non Zero PPM If difference is Less than 10 ppm select Ramped Exit from Hold over More than 10 ppm select Ramped input switching and Ramped Exit from Holdover Select Ramped input switching and Ramped Exit from Holdover Table 5 7 Ramped Input Switching Control Registers Setting Name Hex Address Bit Field Function RAMP_SWITCH_EN_PLLA 0x04A6 3 Enable frequency ramping on an input switch ...

Page 27: ...MHz with a maximum of 2 missing cycles out of every 8 Gapped input clocks are not recommended for use with Hit less Switching as the output phase transients may be significantly higher When properly configured locking to a gapped clock will not trigger the LOS OOF and LOL fault monitors Clock switching between gapped clocks may violate the hitless switching specification for a maximum phase transi...

Page 28: ...itter will increase The following figure shows the effect of a low slew rate on RMS jitter for a differential clock input It shows the relative increase in the amount of RMS jitter due to slow rise time and is not intended to show absolute jitter values 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 0 100 200 300 400 500 600 Relateive Jitter Input Slew V us IN_X Slew Rate in Differential Mode JTYP Figure 5 5 Eff...

Page 29: ...Of Lock LOL indicator asserted when the DSPLL loses synchronization with its reference input Si5397 IN3 IN3 XB XA OSC LOS DSPLL A PD LPF M LOL DSPLL B PD LPF M LOL DSPLL C PD LPF M LOL DSPLL D PD LPF M LOL IN1 IN1 IN2 IN2 IN0 IN0 Precision Fast OOF LOS Precision Fast OOF LOS Precision Fast OOF LOS Precision Fast OOF LOS P0n P0d P1n P1d P2n P2d P3n P3d Figure 5 6 Fault Monitors Si5397 96 Reference ...

Page 30: ...us for each of the monitors is accessible by reading a status register The live LOS register always displays the current LOS state and a sticky register when set always stays asserted until cleared by the user LOS en Monitor LOS LOS Sticky Live Figure 5 8 LOS Status Indicators A LOS monitor is also available to ensure that the external crystal or reference clock is valid By default the output cloc...

Page 31: ...e This OOF reference can be selected as either XA XB pins Any input clock IN0 IN1 IN2 IN3 The final OOF status is determined by the combination of both a precise OOF monitor and a fast OOF monitor as shown in the figure directly below An option to disable either monitor is also available The live OOF register always displays the current OOF state and its sticky register bit stays asserted until cl...

Page 32: ...s will remain asserted when an OOF event oc curs until cleared Writing a zero to a sticky bit will clear it OOF 3 2 1 0 _INTR_MSK 0x0018 7 4 0x0018 7 4 Marks OOF from generating INTRb interrupt for IN3 IN0 0 Allow OOF interrupt default 1 Mask ignore OOF for interrupt OOF Monitor Control and Settings OOF_REF_SEL 0040 2 0 0040 2 0 This selects the clock that the OOF monitors use as their 0 ppm refer...

Page 33: ...tatus Indicators The LOL frequency monitors have an adjustable sensitivity which is register configurable from 0 1 ppm to 10000 ppm CBPro provides a wide range of set and clear thresholds for the LOL function Having two separate frequency monitors allows for hysteresis to help prevent chattering of LOL status An example configuration of the LOL set and clear thresholds is shown below Phase Detecto...

Page 34: ..._THR_PLL D C B A 00A0 7 0 00A1 7 0 00A0 7 0 Configures the loss of lock clear thresholds for DSPLL A B C D LOL_CLR_DE LAY_DIV256_PLL D C B A 00A4 7 0 00B6 7 0 00A4 7 0 00AC 7 0 This is a 29 bit register that configures the delay value for the LOL Clear delay Selectable from 4 ns to over 500 seconds This value depends on the DSPLL fre quency configuration and loop bandwidth It is calcula ted using ...

Page 35: ...g the INTR pin LOSXAXB_INTR_MSK 0017 1 0017 1 Prevents XAXB LOS from asserting the INTR pin LOL_INTR_MSK_PLL D C B A 0019 3 0 0019 1 0 Prevents DSPLL D C B A LOL from asserting the INTR pin HOLD_INTR_MSK_PLL D C B A 0019 7 4 0019 5 4 Prevents DSPLL D C B A HOLD from asserting the INTR pin INTR LOL_INTR_MSK_PLL D A OOF 3 0 _INTR_MSK LOS 3 0 _INTR_MSK CAL_FLG_PLL D A HOLD_INTR_MSK_PLL D A LOSXAXB_FL...

Page 36: ... register bits after inverting the _MSK bit values If the result is a logic one then the _FLG bit will cause an inter rupt For example if LOS_FLG 0 is high and LOS_INTR_MSK 0 is low then the INTR pin will be active low and cause an interrupt If LOS 0 is zero and LOS_MSK 0 is one writing a zero to LOS_MSK 0 will clear the interrupt assuming that there are no other interrupt sources If LOS 0 is high...

Page 37: ...ferential signal formats including LVPECL LVDS HCSL with CML com patible amplitudes In addition to supporting differential signals any of the outputs can be configured as dual single ended LVCMOS 3 3 V 2 5 V or 1 8 V providing up to 16 single ended outputs or any combination of differential and single ended outputs Si5397 96 Reference Manual Outputs silabs com Building a more connected world Rev 0...

Page 38: ... VDDO4 OUT4 R5 OUT5 VDDO5 OUT5 R6 OUT6 VDDO6 OUT6 R7 OUT7 VDDO7 OUT7 Figure 6 1 MultiSynth to Output Driver Crosspoint The figure above is used to set up the routing from the MultiSynth frequency selection to the output Table 6 1 Output Driver Crosspoint Configuration Registers Setting Name Hex Address Bit Field Function Si5397A B Si5397C D Si5396 OUT0_MUX_SEL OUT1_MUX_SEL OUT2_MUX_SEL OUT3_MUX_SE...

Page 39: ...k should not be placed next to a 156 25 MHz clock If the jitter integration bandwidth goes up to 20 MHz then keep adjacent frequencies at least 20 MHz apart 2 Adjacent frequency values that are integer multiples of one another are allowed and these outputs should be grouped together when possible Noting that because 155 52 MHz x 4 622 08 MHz it is okay to place the pair of these frequency values c...

Page 40: ... 3 2 5 or 1 8 V drivers providing up to 8 for the Si5396 single ended outputs or any combination of differential and single ended outputs Note also that CMOS output can create much more crosstalk than differential outputs so extra care must be taken in their pin replacement so that other clocks that need the lowest jitter are not on nearby pins See AN862 Optimizing Jitter Performance in Next Gener...

Page 41: ...D 1 3V 50 50 OUTx OUTxb VDDO 3 3V 2 5V 50 50 100 OUTx OUTxb LVDS VDDO 3 3V 2 5V 1 8V 100 50 50 Internally self biased OUTx OUTxb LVDS VDDO 3 3V 2 5V 1 8V LVPECL VDDO 3 3V 2 5V VDDRX R1 R2 3 3 V 2 5 V 1 8 V 442 332 243 56 2 59 0 63 4 For VCM 0 35 V All caps should have 5 ohms capacitive reactance at the clock output frequency 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF 0 1uF Figure 6 2 Supported Differential Out...

Page 42: ...ging from 400 mVpp_se to 1600 mVpp_se in increments of 200 mV The output driver is in high impedance mode and sup ports standard 50 Ω PCB traces Any of the terminations shown in Figure 6 2 Supported Differential Output Terminations on page 41 are supported The use of High Swing mode will result in larger pk pk output swings that draw less power The trade off will be slower rise and fall times Vpp_...

Page 43: ... Table 6 10 Settings for LVDS LVPECL and HCSL on page 46 for more information 6 4 4 LVCMOS Output Terminations LVCMOS outputs are dc coupled as shown in Figure 6 4 LVCMOS Output Terminations on page 43 3 3V 2 5V 1 8V LVCMOS VDDO 3 3V 2 5V 1 8V 50 Rs 50 Rs DC Coupled LVCMOS OUTx OUTx Figure 6 4 LVCMOS Output Terminations 6 4 5 LVCMOS Output Impedance and Drive Strength Selection Each LVCMOS driver ...

Page 44: ...2_CMOS_DRV OUT3_CMOS_DRV OUT4_CMOS_DRV OUT5_CMOS_DRV OUT6_CMOS_DRV OUT7_CMOS_DRV 0109 7 6 0113 7 6 0118 7 6 011D 7 6 0127 7 6 012C 7 6 0131 7 6 013B 7 6 0109 7 6 011D 7 6 0127 7 6 012C 7 6 0118 7 6 011D 7 6 0127 7 6 012C 7 6 LVCMOS output impedance 6 4 6 LVCMOS Output Signal Swing The signal swing VOL VOH of the LVCMOS output drivers is set by the voltage on the VDDO pins Each output driver has it...

Page 45: ...V OUT4_INV OUT5_INV OUT6_INV OUT7_INV 010B 7 6 0115 7 6 011A 7 6 011F 7 6 0129 7 6 012E 7 6 0133 7 6 013D 7 6 010B 7 6 011F 7 6 0129 7 6 012E 7 6 0115 7 6 011A 7 6 0129 7 6 012E 7 6 Controls output polarity of the OUTx and OUTx pins when in LVCMOS mode Selections are OUTx_IN V Register Settings OUTx OUTx Comment 0 0 CLK CLK Both in phase de fault 0 1 CLK CLK OUTx inverted 1 0 CLK CLK OUTx and OUTx...

Page 46: ... the various supported standards are shown in Table 6 10 Settings for LVDS LVPECL and HCSL on page 46 Table 6 10 Settings for LVDS LVPECL and HCSL OUTx_FORMAT1 Standard VDDO Volts OUTx_CM Decimal OUTx_AMPL Decimal 001 Normal Differential LVPECL 3 3 11 6 001 Normal Differential LVPECL 2 5 11 6 002 Low Power Differential LVPECL 3 3 11 3 002 Low Power Differential LVPECL 2 5 11 3 001 Normal Different...

Page 47: ...for an application However CML is not a defined standard and hence the amplitude of a CML signal for one receiver may be different than that of another receiver When the output amplitude needs to be different than standard LVDS or LVPECL the Common Mode Voltage settings must be set as shown in Table 6 11 Output Differential Common Mode Voltage Settings on page 47 No settings other than these are s...

Page 48: ... held high disabled then all assigned outputs will be disabled regardless of the state of this register bit OUT0_OE OUT1_OE OUT2_OE OUT3_OE OUT4_OE OUT5_OE OUT6_OE OUT7_OE 0108 1 0112 1 0117 1 011C 1 0126 1 012B 1 0130 1 013A 1 0108 1 011C 1 0126 1 012B 1 0012 1 0117 1 0126 1 012B 1 Allows enabling disabling individual output driv ers Note that the OE pin must be held low in or der to enable an ou...

Page 49: ... assigned outputs will be disabled regardless of the state of this register bit OUT0_OE OUT1_OE OUT2_OE OUT3_OE OUT4_OE OUT5_OE OUT6_OE OUT7_OE 0108 1 0112 1 0117 1 011C 1 0126 1 012B 1 0130 1 013A 1 0108 1 011C 1 0126 1 012B 1 0012 1 0117 1 0126 1 012B 1 Allows enabling disabling individual output driv ers Note that the OE pin must be held low in or der to enable an output with these register bit...

Page 50: ...l Registers Setting Name Hex Address Bit Field Function Si5397A B Si5397C D Si5396 OUT0_SYNC_EN OUT1_SYNC_EN OUT2_SYNC_EN OUT3_SYNC_EN OUT4_SYNC_EN OUT5_SYNC_EN OUT6_SYNC_EN OUT7_SYNC_EN 0109 3 0113 3 0118 3 011D 3 0127 3 012C 3 0131 3 013B 3 0109 3 011D 3 0127 3 012C 3 0113 3 0118 3 0127 3 012C 3 Selects Synchronous or Asynchronous output disable 1 synchronous 0 asynchronous De fault is synchrono...

Page 51: ...ould have fractional M division enabled by setting the appropriate M_FRAC_EN_PLLx 0x3B for proper operation Note DCO mode is not available when in free run or when in holdover A large freq step can assert LOL on the relevant DSPLL The step sizes and frequency of operation need to be considered with the LOL settings and BW Table 7 1 Fractional M Divider Enable Controls Setting Name Hex Address Bit ...

Page 52: ...NC FDEC pins on the Si5397 are unused the FDEC pin must be pulled down with an external pull down resistor or jumper The FINC pin has an internal pull down and may be left unconnected when not in use Table 7 2 0x0020 DSPLL_SEL 1 0 Control of FINC FDEC for DCO Reg Address Bit Field Type Name Description 0x0020 0 R W FSTEP_PLL_SIN GLE 0 DSPLL_SEL 1 0 pins and bits are disabled 1 DSPLL_SEL 1 0 pins o...

Page 53: ...y Step Word DSPLL B LPF PD Mn_B Md_B Frequency Step Word 0x0423 0x0429 0x0523 0x0529 0x0623 0x0629 0x0724 0x072A DSPLL_SEL0 DSPLL_SEL1 FDEC FINC Si5397 Figure 7 1 Controlling the DCO Mode By Pin Control Si5397 96 Reference Manual Digitally Controlled Oscillator DCO Mode silabs com Building a more connected world Rev 0 9 53 ...

Page 54: ...de should have fractional M division enabled by setting the appropriate M_FRAC_EN_PLLx 0x3B for proper operation See AN909 DCO Application with the Jitter Attenuators for related information 0x0422 FSW_MASK_A DSPLL A LPF PD Mn_A Md_A Frequency Step Word 0x0522 FSW_MASK_B 0x0622 FSW_MASK_C DSPLL C LPF PD Mn_C Md_C Frequency Step Word DSPLL D LPF PD Mn_D Md_D Frequency Step Word 0x0723 FSW_MASK_D DS...

Page 55: ...on and is easily calculated us ing ClockBuilder Pro utility M_FSTEPW_PLLB 0523 7 0 0529 7 0 0523 7 0 0529 7 0 M_FSTEPW_PLLC 0623 7 0 0629 7 0 M_FSTEPW_PLLD 0724 7 0 072A 7 0 M_FSTEP_MSK_PLLA 0422 0 0422 0 This mask bit determines if a FINC or FDEC affects DSPLL A B C D 0 FINC FDEC will increment decre ment the FSTEPW to the DSPLL 1 Ignores FINC FDEC M_FSTEP_MSK_PLLB 0522 0 0522 0 M_FSTEP_MSK_PLLC ...

Page 56: ...ly recommended to avoid dynamically changing the M divider denominator Mx_DEN as in some cases a small output phase shift may be observed when the update becomes active However by using the proper combination of settings for the particular frequency plan it is possible to avoid this entirely If your application requires dynamic changes to an M divider denominator contact Silicon Labs at https www ...

Page 57: ... up Frequency On The Fly with CLI tool is included in these two documents CBPro Tools Support for In System Programming CLI User s Guide Figure 8 1 CBPro Tools Support for In System Programming The following steps outline the procedure to initiate Frequency On The Fly 1 Create CBPro project as base frequency plan 2 Create text files detailing the input output frequency bandwidth and or LOL OOF thr...

Page 58: ... of OOF LOS or bandwidth A plan file only has to reconfigure at least one of the following Clock output frequency Clock input frequency DSPLL bandwidth LOL thresholds OOF thresholds On multi DSPLL devices frequency on the fly can only be performed on a PLL that has exclusive clock inputs That is an input to the FOTF PLL cannot also be MUXed to another DSPLL For example given the following configur...

Page 59: ...L pin High IO_VDD_SEL 0 IO_VDD_SEL 0 I2C_SEL pin Low SPI HOST 1 8V SDI SDO CSb CSb SDO SDI SCLK SCLK Clock IC I2 C HOST 1 8V VDDA SCLK SDA 1 8V VDD 1 8V 3 3V SPI HOST 1 8V SDIO SDIO CSb CSb SCLK SCLK SPI_3WIRE 0 SPI 4 Wire SPI 3 Wire I2C_SEL pin Low SPI_3WIRE 1 IO_VDD_SEL 0 IO_VDD_SEL 1 IO_VDD_SEL 1 IO_VDD_SEL 1 SCLK SDA Default Default VDDA VDD 1 8V 3 3V Default VDDA VDD 1 8V 3 3V SPI HOST 3 3V S...

Page 60: ...t write the IO_VDD_SEL configuration bit to the VDDA option This will ensure that both the host and the serial interface are operating at the optimum voltage thresholds SPI_3WIRE 0x002B 3 The SPI_3WIRE configuration bit selects the option of 4 wire or 3 wire SPI communication By default this configuration bit is set to the 4 wire option In this mode the Si5397 96 will accept write commands from a ...

Page 61: ...ts as shown in the following figure Slave Address 1 1 0 1 1 A0 0 1 2 3 4 5 6 A1 Figure 9 3 7 bit I2C Slave Address Bit Configuration Data is transferred MSB first in 8 bit words as specified by the I2C specification A write command consists of a 7 bit device slave address a write bit an 8 bit register address and 8 bits of data as shown in Figure 9 6 SPI Interface Connections on page 63 A write bu...

Page 62: ...Addr 6 0 Data 7 0 A P N Data 7 0 Host Clock IC Host Clock IC Figure 9 5 I2C Read Operation The SMBUS interface requires a timeout The error flags are found in the registers listed below Table 9 2 SMBus Timeout Error Bit Indicators Register Name Hex Address Bit Field Function SMBUS_TIMEOUT 0x000C 5 1 if there is a SMBus timeout error SMBUS_TIME OUT_FLG 0x0011 5 1 if there is a SMBus timeout error S...

Page 63: ... CSb high 3 There is no limit to the number of data bytes that follow the Burst Write Command but the address will wrap around to zero in the byte after address 255 is written Writing or reading data consist of sending a Set Address command followed by a Write Data or Read Data command The Write Data Address Increment or Read Data Address Increment commands are available for cases where multiple b...

Page 64: ...ite Data Addr Inc Figure 9 7 Example Writing Three Data Bytes using the SPI Write Commands Set Address and Read Data Address Increment Set Address and Read Data Set Addr Addr 7 0 Read Data Data 7 0 Set Addr Addr 7 0 Read Data Data 7 0 Set Addr Addr 7 0 Read Data Data 7 0 Data 7 0 Set Addr Addr 7 0 Data 7 0 Clock IC Host Clock IC Host Read Data Addr Inc Read Data Addr Inc Data 7 0 Read Data Addr In...

Page 65: ...n page 67 and Figure 9 12 SPI Burst Data Write Instruction Timing on page 67 Set Address Instruction Base Address CS SCLK SDI SDO SDIO 4 Wire 3 Wire Set Address Command 95 ns Previous Command Next Command 1 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 6 7 1 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 6 7 Clock IC Host Clock IC Host Don t Care High Impedance 7 7 95 ns Figure 9 9 SPI Set Address Command Timing Si5397 96 Ref...

Page 66: ...d Next Command 1 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 6 7 1 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 6 7 Clock IC Host Clock IC Host Don t Care High Impedance 95 ns 95 ns Figure 9 10 SPI Write Data and Write Data Address Increment Instruction Timing Si5397 96 Reference Manual Serial Interface silabs com Building a more connected world Rev 0 9 66 ...

Page 67: ...vious Command SDI 1 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 0 1 2 3 4 5 6 Clock IC Host Clock IC Host Don t Care High Impedance 1st data byte base address 6 Next Command 6 7 7 7 7 7 7 7 95 ns 95 ns Figure 9 12 SPI Burst Data Write Instruction Timing Note that for all SPI communication the chip select CS must be high for the mini...

Page 68: ...t drive strength to drive a 100 Ω or 50 Ω load For this reason place the TCXO as close to the Si5397 96 as possible to minimize PCB trace length In addition ensure that both the Si5397 96 and the TCXO are both connected directly to the ground plane Figure 10 1 XAXB Crystal Resonator and External Reference Clock Connection Options on page 68 shows the recommended method of connecting a clipped sine...

Page 69: ... to use an external refer ence oscillator The internal crystal loading capacitors CL are disabled when an external clock source is selected 10 3 2 PXAXB Pre scale Divide Ratio for Reference Clock Register Table 10 2 XAXB Pre Scale Divide Ratio Register Setting Name Hex Address Bit Field Function Si5397 96 PXAXB 0x0206 1 0 Sets the XAXB input divider value according to the table below The following...

Page 70: ...ply depopulate the crystal and replace the external crystal device with the internal crystal version It is important to note that a new CBPro plan is required for the integrated crystal variant For more information please contact Silicon Labs support For specifications of the internal crystal please refer to the data sheet During the initial power up the integrated crystal quickly settles down to ...

Page 71: ... eight layers Layer 1 device layer with low speed CMOS control status signals Layer 2 crystal shield applies to external reference devices only Layer 3 ground plane Layer 4 power distribution Layer 5 power routing layer Layer 6 input clocks Layer 7 output clocks layer Layer 8 ground layer The 64 pin QFN crystal guidelines show the top layer layout of the Si5397 device mounted on the top PCB layer ...

Page 72: ...next layer down is shown in Figure 12 2 Zoom View Crystal Shield Layer Below the Top Layer Layer 2 on page 73 4 Minimize traces adjacent to the crystal oscillator area especially if they are clocks or frequently toggling digital signals 5 In general do not route GND power planes traces or locate components on the other side below the crystal GND shield As an exception if it is absolutely necessary...

Page 73: ...ayer 2 using vias to avoid crosstalk As soon as the clock inputs are on layer 2 they have a ground shield above below and on the sides for protection Figure 12 3 Crystal Ground Plane Layer 3 on page 74 is the ground plane and shows a void underneath the crystal shield Figure 12 4 Power Plane Layer 4 on page 75 is a power plane and shows the clock output power supply traces The void underneath the ...

Page 74: ...Figure 12 3 Crystal Ground Plane Layer 3 Si5397 96 Reference Manual Crystal XO and Device Circuit Layout Recommendations silabs com Building a more connected world Rev 0 9 74 ...

Page 75: ...ing on Power Plane Layer 5 on page 76 shows layer 5 which is the power plane with the power routed to the clock output power pins Si5397 96 Reference Manual Crystal XO and Device Circuit Layout Recommendations silabs com Building a more connected world Rev 0 9 75 ...

Page 76: ...ower Plane Layer 5 Figure 12 6 Ground Plane Layer 6 on page 77 is another ground plane similar to layer 3 Si5397 96 Reference Manual Crystal XO and Device Circuit Layout Recommendations silabs com Building a more connected world Rev 0 9 76 ...

Page 77: ...Figure 12 6 Ground Plane Layer 6 Si5397 96 Reference Manual Crystal XO and Device Circuit Layout Recommendations silabs com Building a more connected world Rev 0 9 77 ...

Page 78: ...a ground flooding between the clock output pairs to avoid crosstalk There should be a line of vias through the ground flood on either side of the output clocks to ensure that the ground flood immediately next to the differential pairs has a low inductance path to the ground plane on layers 3 and 6 Figure 12 7 Output Clock Layer Layer 7 Si5397 96 Reference Manual Crystal XO and Device Circuit Layou...

Page 79: ...ected An additional benefit of the internal crystal is that is does NOT need a crystal shield or voids on the PCB layers beneath the crystal It is recommended to minimize traces adjacent to the chip especially if there are clocks or frequently toggling digital signals to avoid coupling of these signals into the device Si5397 96 Reference Manual Crystal XO and Device Circuit Layout Recommendations ...

Page 80: ...uld always be routed on an internal layer with ground reference planes directly above and below The plane that has the routing for the output clocks should have ground flooded near the clock traces to further isolate the clocks from noise and other signals 12 3 1 Si5396 XO Guidelines For devices that use an external reference like an XO pins X1 and X2 should not be connected to ground and should b...

Page 81: ...oute GND power planes traces or locate components on the other side below the crystal GND shield As an exception if it is absolutely necessary to use the area on the other side of the board for layout or routing then place the next refer ence plane in the stack up at least two layers away or at least 0 05 inches away The Si5396 should have all layers underneath the ground shield removed if possibl...

Page 82: ...re 12 11 Ground Plane Layer 3 on page 83 is the ground plane and shows a void underneath the crystal shield Si5397 96 Reference Manual Crystal XO and Device Circuit Layout Recommendations silabs com Building a more connected world Rev 0 9 82 ...

Page 83: ...r Supply Traces Layer 4 on page 84 is a power plane showing the clock output power supply traces The void underneath the crystal shield is continued Si5397 96 Reference Manual Crystal XO and Device Circuit Layout Recommendations silabs com Building a more connected world Rev 0 9 83 ...

Page 84: ...ayer 5 on page 85 shows layer 5 and the clock input traces Similar to the clock output traces they are routed to an inner layer and surrounded by ground to avoid crosstalk Si5397 96 Reference Manual Crystal XO and Device Circuit Layout Recommendations silabs com Building a more connected world Rev 0 9 84 ...

Page 85: ...e shield Layer 6 and layer 1 are mainly used for low speed CMOS control and status signals for which crosstalk is not a significant issue PCB ground can be placed under the XTAL Ground shield X1 X2 as long as the PCB ground is at least 0 05 inches below it Si5397 96 Reference Manual Crystal XO and Device Circuit Layout Recommendations silabs com Building a more connected world Rev 0 9 85 ...

Page 86: ...n LGA Si5396 Layout Recommendations The crystal is integrated inside the package so leave XA XB X1 and X2 unconnected An additional benefit of the internal crystal is that is does NOT need a crystal shield or voids on the PCB layers beneath the crystal It is recommended to minimize traces adjacent to the chip especially if there are clocks or frequently toggling digital signals to avoid coupling o...

Page 87: ...n series with each supply to enable additional filtering if needed 13 3 Power Supply Sequencing Four classes of supply voltages exist on the Si5397 96 1 VDD 1 8 V Core digital supply 2 VDDA 3 3 V Analog supply 3 VDDOx 1 8 2 5 3 3 V 5 Clock output supply 4 VDDS 1 8 3 3V 5 Digital I O supply There is no requirement for power supply sequencing unless the output clocks are required to be phase aligned...

Page 88: ... to the internal ground plane of the PCB Use no fewer than 25 vias from the center pad to a ground plane under the device In general more vias will perform better Having the ground plane near the top layer will also help to minimize the via inductance from the device to ground and maximize the heat transfer away from the device Si5397 96 Reference Manual Power Management silabs com Building a more...

Page 89: ... Pro software Many customers prefer to order devices which are factory preprogrammed for a particular application that includes specifying the XA XB reference frequency type the clock input frequencies the clock output frequencies as well as the other options such as auto matic clock selection loop BW etc The ClockBuilder software is required to select among all of these options and to produce a p...

Page 90: ...zed hierarchically below To find the relevant information for your application first choose the section corresponding to the base part number Si5397 Si5396 for your design Then choose the section under that for the page containing the desired register s Default register contents and settings differ for each device part number or OPN This information may be found by searching for the Custom OPN for...

Page 91: ...ion 0x0002 7 0 R PN_BASE 0x47 Four digit base part number one nibble per digit Example Si5397A A GM The base part num ber OPN is 5397 which is stored in this regis ter 0x0003 15 8 R PN_BASE 0x53 Table 15 4 0x0004 Device Grade Reg Address Bit Field Type Setting Name Description 0x0004 7 0 R GRADE One ASCII character indicating the device speed synthesis mode 0 A 1 B 2 C 3 D 10 J 11 K 12 L 13 M Refe...

Page 92: ...an and all other operating characteristics defined by the user s ClockBuilder Pro project file Si5397C A GM Applies to a base or blank OPN device Base devices are factory pre programmed to a specific base part type e g Si5397 but exclude any user defined frequency plan or other user defined operating characteristics selected in ClockBuilder Pro Table 15 8 0x000B I2C Address Reg Address Bit Field T...

Page 93: ...g Name Description 0x000E 3 0 R LOL_PLL D A 1 if the DSPLL is out of lock 0x000E 7 4 R HOLD_PLL D A 1 if the DSPLL is in holdover or free run DSPLL_A corresponds to bit 0 4 DSPLL_B corresponds to bit 1 5 DSPLL_C corresponds to bit 2 6 DSPLL_D corresponds to bit 3 7 Table 15 12 0x000F INCAL Status Reg Address Bit Field Type Setting Name Description 0x000F 7 4 R CAL_PLL D A 1 if the DSPLL internal c...

Page 94: ...G 0x0012 3 OOF_FLG 0x0012 7 Table 15 15 0x0013 Holdover and LOL Flags Reg Address Bit Field Type Setting Name Description 0x0013 3 0 R W LOL_FLG_PLL D A 1 if the DSPLL was unlocked 0x0013 7 4 R W HOLD_FLG_PLL D A 1 if the DSPLL was in holdover or freerun Sticky flag versions of address 0x000E DSPLL_A corresponds to bit 0 4 DSPLL_B corresponds to bit 1 5 DSPLL_C corresponds to bit 2 6 DSPLL_D corre...

Page 95: ...Input 0 IN0 corresponds to LOS_IN_INTR_MSK 0x0018 0 OOF_IN_INTR_MSK 0x0018 4 Input 1 IN1 corresponds to LOS_IN_INTR_MSK 0x0018 1 OOF_IN_INTR_MSK 0x0018 5 Input 2 IN2 corresponds to LOS_IN_INTR_MSK 0x0018 2 OOF_IN_INTR_MSK 0x0018 6 Input 3 IN3 corresponds to LOS_IN_INTR_MSK 0x0018 3 OOF_IN_INTR_MSK 0x0018 7 These are the interrupt mask bits for the OOF and LOS flags in register 0x0012 If a mask bit...

Page 96: ...which means self clearing Unlike SOFT_RST_ALL the SOFT_RST_PLLx bits do not update the loop BW values If these have changed the update can be done by writing to BW_UPDATE_PLLA BW_UPDATE_PLLB BW_UPDATE_PLLC and BW_UPDATE_PLLD at addresses 0x0414 0x514 0x0614 and 0x0715 Table 15 23 0x001D FINC FDEC Reg Address Bit Field Type Setting Name Description 0x001D 0 S FINC 0 No effect 1 A rising edge will c...

Page 97: ...M divider 3 DSPLL D M divider By default ClockBuilder Pro sets OE0 controlling all outputs OUTALL_DISABLE_LOW 0x0102 0 must be high enabled to observe the effects of OE0 Note that the OE0 register bits active high have inverted logic sense from the pins active low Table 15 26 0x002B SPI 3 vs 4 Wire Reg Address Bit Field Type Setting Name Description 0x002B 3 R W SPI_3WIRE 0 For 4 wire SPI 1 For 3 ...

Page 98: ...or Input 0 given a particular frequency plan Table 15 30 0x0030 0x0031 LOS1 Trigger Threshold Reg Address Bit Field Type Setting Name Description 0x0030 7 0 R W LOS1_TRG_THR 16 bit Threshold Value 0x0031 15 8 R W LOS1_TRG_THR ClockBuilder Pro calculates the correct LOS register threshold trigger value for Input 1 given a particular frequency plan Table 15 31 0x0032 0x0033 LOS2 Trigger Threshold Re...

Page 99: ...escription 0x003A 7 0 R W LOS2_CLR_THR 16 bit Threshold Value 0x003B 15 8 R W LOS2_CLR_THR ClockBuilder Pro calculates the correct LOS register clear threshold value for Input 2 given a particular frequency plan Table 15 36 0x003C 0x003D LOS3 Clear Threshold Reg Address Bit Field Type Setting Name Description 0x003C 7 0 R W LOS3_CLR_THR 16 bit Threshold Value 0x003D 15 8 R W LOS3_CLR_THR ClockBuil...

Page 100: ...R W OOF0_SET_THR OOF Set Threshold Range is up to 500 ppm in steps of 1 16 ppm 0x0047 7 0 R W OOF1_SET_THR OOF Set Threshold Range is up to 500 ppm in steps of 1 16 ppm 0x0048 7 0 R W OOF2_SET_THR OOF Set Threshold Range is up to 500 ppm in steps of 1 16 ppm 0x0049 7 0 R W OOF3_SET_THR OOF Set Threshold Range is up to 500 ppm in steps of 1 16 ppm Table 15 42 0x004A 0x004D Out of Frequency Clear Th...

Page 101: ...2 IN1 and IN0 when the fast control is enabled The value in each of the register is 1 value x 1000 ppm ClockBuilder Pro is used to determine the values for these registers Table 15 46 0x0055 0x0058 Fast Out of Frequency Clear Threshold Reg Address Bit Field Type Setting Name Description 0x0055 3 0 R W FAST_OOF0_CLR_ THR 1 value x 1000 ppm 0x0056 3 0 R W FAST_OOF1_CLR_ THR 1 value x 1000 ppm 0x0057...

Page 102: ...ld Type Setting Name Description 0x005E 7 0 R W OOF1_RATIO_REF Values calculated by CBPro 0x005F 15 8 R W OOF1_RATIO_REF 0x0060 23 16 R W OOF1_RATIO_REF 0x0061 25 24 R W OOF1_RATIO_REF Table 15 50 0x0062 0x0065 OOF2 Ratio for Reference Reg Address Bit Field Type Setting Name Description 0x0062 7 0 R W OOF2_RATIO_REF Values calculated by CBPro 0x0063 15 8 R W OOF2_RATIO_REF 0x0064 23 16 R W OOF2_RA...

Page 103: ... W LOL_FST_DET WIN_SEL_PLLC 0x0094 7 4 R W LOL_FST_DET WIN_SEL_PLLD Table 15 54 0x0095 Fast LOL Detection Value Reg Address Bit Field Type Setting Name Description 0x0095 1 0 R W LOL_FST_VAL WIN_SEL_PLLA Values calculated by CBPro 0x0095 3 2 R W LOL_FST_VAL WIN_SEL_PLLB 0x0095 5 4 R W LOL_FST_VAL WIN_SEL_PLLC 0x0095 7 6 R W LOL_FST_VAL WIN_SEL_PLLD Table 15 55 0x0096 0x0097 Fast LOL Set Threshold ...

Page 104: ... 0 To disable LOL 1 To enable LOL 0x009A 1 LOL_SLOW_EN_P LLB 0 To disable LOL 1 To enable LOL 0x009A 2 LOL_SLOW_EN_P LLC 0 To disable LOL 1 To enable LOL 0x009A 3 LOL_SLOW_EN_P LLD 0 To disable LOL 1 To enable LOL Table 15 58 0x009B 0x009C Slow LOL Detection Value Reg Address Bit Field Type Setting Name Description 0x009B 3 0 R W LOL_SLW_DET WIN_SEL_PLLA Values calculated by CBPro 0x009B 7 4 R W L...

Page 105: ...09F 3 0 R W LOL_SLW_SET_TH R_PLLC Configures the loss of lock set thresholds See list be low for selectable values 0x009F 7 4 R W LOL_SLW_SET_TH R_PLLD Configures the loss of lock set thresholds See list be low for selectable values The following are the LOL_SLW_SET_THR_PLLx thresholds for the value that is placed in the four bits for DSPLLs 0 0 1 ppm 1 0 3 ppm 2 1 ppm 3 3 ppm 4 10 ppm 5 30 ppm 6 ...

Page 106: ... ppm 10 10000 ppm 11 15 Reserved Table 15 64 0x00A2 LOL Timer Enable Reg Address Bit Field Type Setting Name Description 0x00A2 0 1 2 3 R W LOL_TIM ER_EN_PLLA LOL_TIM ER_EN_PLLB LOL_TIM ER_EN_PLLC LOL_TIM ER_EN_PLLD Enable Delay for LOL Clear 0 Disable Delay for LOL Clear 1 Enable Delay for LOL Clear Table 15 65 0x00A4 0x00A7 LOL Clear Delay DSPLL A Reg Address Bit Field Type Setting Name Descript...

Page 107: ...AY_DIV256_PLLC 0x00B1 28 24 R W LOL_CLR_DE LAY_DIV256_PLLC Table 15 68 0x00B3 0x00B6 LOL Clear Delay DSPLL D Reg Address Bit Field Type Setting Name Description 0x00B3 7 0 R W LOL_CLR_DE LAY_DIV256_PLLD 29 bit value Sets the clear timer 0x00AA 15 8 R W LOL_CLR_DLY for LOL CBPro sets this value 0x00B4 15 8 R W LOL_CLR_DE LAY_DIV256_PLLD 0x00B5 23 16 R W LOL_CLR_DE LAY_DIV256_PLLD 0x00B6 28 24 R W L...

Page 108: ...dress Bit Field Type Setting Name Description 0x00E6 7 0 R W FASTLOCK_EX TEND_PLLA 29 bit value Set by CBPro to minimize the phase tran sients when switching the PLL bandwidth See FAST LOCK_EXTEND_SCL_PLLx 0x00E7 15 8 R W FASTLOCK_EX TEND_PLLA 0x00E8 23 16 R W FASTLOCK_EX TEND_PLLA 0x00E9 28 24 R W FASTLOCK_EX TEND_PLLA Table 15 74 0x00EA 0x00ED FASTLOCK_EXTEND_PLLB Reg Address Bit Field Type Sett...

Page 109: ...mize the phase tran sients when switching the PLL bandwidth See FAST LOCK_EXTEND_SCL_PLLx 0x00F3 15 8 R W FASTLOCK_EX TEND_PLLD 0x00F4 23 16 R W FASTLOCK_EX TEND_PLLD 0x00F5 28 24 R W FASTLOCK_EX TEND_PLLD Table 15 77 0x00F6 Reg Address Bit Field Type Name Description 0x00F6 0 R REG_0XF7_INT R Set by CBPro 0x00F6 1 R REG_0XF8_INT R Set by CBPro 0x00F6 2 R REG_0XF9_INT R Set by CBPro Table 15 78 0x...

Page 110: ...Name Description 0x00FE 7 0 R DEVICE_READY Ready Only byte to indicate device is ready When read data is 0x0F one can safely read write registers This register is repeated on every page so that a page write is not ever required to read the DEVICE_READY sta tus WARNING Any attempt to read or write any register other than DEVICE_READY before DEVICE_READY reads as 0x0F may corrupt the NVM programming...

Page 111: ... Type Setting Name Description 0x0108 0x0112 0x0117 0x011C 0x0126 0x012B 0x0130 0x013A 0 R W OUT0_PDN OUT1_PDN OUT2_PDN OUT3_PDN OUT4_PDN OUT5_PDN OUT6_PDN OUT7_PDN 0 To power up the regulator 1 To power down the regulator When powered down output pins will be high impe dance with a light pull down effect 0x0108 0x0112 0x0117 0x011C 0x0126 0x012B 0x0130 0x013A 1 R W OUT0_OE OUT1_OE OUT2_OE OUT3_OE...

Page 112: ...3B Output Format Reg Address Bit Field Type Setting Name Description 0x0109 0x0113 0x0118 0x011D 0x0127 0x012C 0x0131 0x013B 2 0 R W OUT0_FORMAT OUT1_FORMAT OUT2_FORMAT OUT3_FORMAT OUT4_FORMAT OUT5_FORMAT OUT6_FORMAT OUT7_FORMAT 0 Reserved 1 Differential Normal mode 2 Differential Low Power mode 3 Reserved 4 LVCMOS single ended 5 LVCMOS pin only 6 LVCMOS pin only 7 Reserved 0x0109 0x0113 0x0118 0x...

Page 113: ... strength see The output drivers are all identical Table 15 85 0x010A 0x0114 0x0119 0x011E 0x0128 0x012D 0x0132 0x0137 Output Amplitude and Common Mode Reg Address Bit Field Type Setting Name Description 0x010A 0x0114 0x0119 0x011E 0x0128 0x012D 0x0132 0x0137 3 0 R W OUT0_CM OUT1_CM OUT2_CM OUT3_CM OUT4_CM OUT5_CM OUT6_CM OUT7_CM OUTx common mode voltage selection This field only applies when OUTx...

Page 114: ...t This selects the source of the output clock 0 DSPLL A 1 DSPLL B 2 DSPLL C 3 DSPLL D 5 7 Reserved 0x010B 0x0115 0x011A 0x011F 0x0129 0x012E 0x0133 0x013D 3 R W OUT0_VDD_SEL_E N OUT1_VDD_SEL_E N OUT2_VDD_SEL_E N OUT3_VDD_SEL_E N OUT4_VDD_SEL_E N OUT5_VDD_SEL_E N OUT6_VDD_SEL_E N OUT7_VDD_SEL_E N 0 Reserved 1 Enable manual OUTx_VDD_SEL 0x010B 0x0115 0x011A 0x011F 0x0129 0x012E 0x0133 0x013D 5 4 R W...

Page 115: ...Disable Source DSPLL Reg Address Bit Field Type Setting Name Description 0x010C 0x0116 0x011B 0x0120 0x012A 0x012F 0x0134 0x013E 2 0 R W OUT0_DIS_SRC OUT1_DIS_SRC OUT2_DIS_SRC OUT3_DIS_SRC OUT4_DIS_SRC OUT5_DIS_SRC OUT6_DIS_SRC OUT7_DIS_SRC Output driver 0 input mux select This selects the source of the output clock 0 DSPLL A squelches output 1 DSPLL B squelches output 2 DSPLL C squelches output 3...

Page 116: ...bled on LOSXAXB 1 All outputs remain enabled during LOSXAXB condi tion 0x0141 7 R W OUT_DIS_MSK_LO S_PFD Set by CBPro Table 15 90 0x0142 Output Disable Loss of Lock PLL Reg Address Bit Field Type Setting Name Description 0x0142 3 0 R W OUT_DIS_MSK_LO L_PLL D A 0 LOL will disable all connected outputs 1 LOL does not disable any outputs 0x0142 7 4 R W OUT_DIS_MSK_H OLD_PLL D A Set by CBPro Bit 0 LOL...

Page 117: ...ers Note that changing these registers during operation may cause indefinite loss of lock unless the guidelines in are followed Table 15 93 0x020E 0x0211 P0 Divider Denominator Reg Address Bit Field Type Setting Name Description 0x020E 7 0 R W P0_DEN 32 bit Integer Number 0x020F 15 8 R W P0_DEN 0x0210 23 16 R W P0_DEN 0x0211 31 24 R W P0_DEN The P1 P2 and P3 divider numerator and denominator follo...

Page 118: ..._PLLB etc as these do not update the Px_NUM or Px_DEN values Table 15 96 0x0231 P0 Factional Division Enable Reg Address Bit Field Type Setting Name Description 0x0231 3 0 R W P0_FRACN_MODE P0 IN0 input divider fractional mode Must be set to 0xB for proper operation 0x0231 4 R W P0_FRAC_EN P0 IN0 input divider fractional enable 0 Integer only division 1 Fractional or Integer division Table 15 97 0...

Page 119: ...Note that changing this register during operation may cause indefinite loss of lock unless the guidelines in are followed Table 15 101 0x023B 0x023E MXAXB Divider Denominator Reg Address Bit Field Type Setting Name Description 0x023B 7 0 R W MXAXB_DEN 32 bit Integer Number 0x023C 15 8 R W MXAXB_DEN 0x023D 23 16 R W MXAXB_DEN 0x023E 31 24 R W MXAXB_DEN The M divider numerator and denominator are se...

Page 120: ...Number 0x024A 0x024C 0x025F 0x0261 R5_REG 24 bit Integer Number 0x024A 0x024C 0x0262 0x0264 R6_REG 24 bit Integer Number 0x024A 0x024C 0x0268 0x026A R7_REG 24 bit Integer Number 0x024A 0x024C Table 15 105 0x026B 0x0272 Design Identifier Reg Address Bit Field Type Setting Name Description 0x026B 7 0 R W DESIGN_ID0 ASCII encoded string defined by ClockBuilder Pro user with user defined space or null...

Page 121: ...c base part type e g Si5397 but exclude any user defined frequency plan or other user defined operating characteristics selected in ClockBuilder Pro Table 15 107 0x027D Reg Address Bit Field Type Setting Name Description 0x027D 7 0 R W OPN_REVISION Table 15 108 0x027E Reg Address Bit Field Type Setting Name Description 0x027E 7 0 R W BASELINE_ID Table 15 109 0x028A 0x028D Reg Address Bit Field Typ...

Page 122: ...s Bit Field Type Setting Name Description 0x0292 3 0 R W OOF_STOP_ON_L OS Set by CBPro 0x0293 3 0 R W OOF_CLEAR_ON_ LOS Set by CBPro Table 15 112 0x0294 0x0295 FASTLOCK EXTEND SCL PLLx Reg Address Bit Field Type Setting Name Description 0x0294 3 0 R W FASTLOCK_EX TEND_SCL_PLLA Scales LOLB_INT_TIMER_DIV256 Set by CBPro 0x0294 7 4 R W FASTLOCK_EX TEND_SCL_PLLB 0x0295 3 0 R W FASTLOCK_EX TEND_SCL_PLL...

Page 123: ...etting Name Description 0x0299 0 R W FAST LOCK_DLY_ON LOL_EN_PLLA Set by CBPro 0x0299 1 R W FAST LOCK_DLY_ON LOL_EN_PLLB 0x0299 2 R W FAST LOCK_DLY_ON LOL_EN_PLLC 0x0299 3 R W FAST LOCK_DLY_ON LOL_EN_PLLD Table 15 116 0x029A 0x029C FASTLOCK_DLY_ONLOL_PLLA Reg Address Bit Field Type Setting Name Description 0x029A 7 0 R W FAST LOCK_DLY_ON LOL_PLLA Set by CBPro 0x029B 15 8 R W FAST LOCK_DLY_ON LOL_P...

Page 124: ... Type Setting Name Description 0x02A0 7 0 R W FAST LOCK_DLY_ON LOL_PLLC Set by CBPro 0x02A1 15 8 R W FAST LOCK_DLY_ON LOL_PLLC 0x02A2 19 16 R W FAST LOCK_DLY_ON LOL_PLLC Table 15 119 0x02A3 0x02A5 FASTLOCK_DLY_ONLOL_PLLD Reg Address Bit Field Type Setting Name Description 0x02A3 7 0 R W FAST LOCK_DLY_ON LOL_PLLD Set by CBPro 0x02A4 15 8 R W FAST LOCK_DLY_ON LOL_PLLD 0x02A5 19 16 R W FAST LOCK_DLY_...

Page 125: ...Setting Name Description 0x02A9 7 0 R W FAST LOCK_DLY_ONSW _PLLB 20 bit value Set by CBPro 0x02AA 15 8 R W FAST LOCK_DLY_ONSW _PLLB 0x02AB 19 16 R W FAST LOCK_DLY_ONSW _PLLB Table 15 122 0x02AC 0x02AE FASTLOCK_DLY_ONSW_PLLC Reg Address Bit Field Type Setting Name Description 0x02AC 7 0 R W FAST LOCK_DLY_ONSW _PLLC 20 bit value Set by CBPro 0x02AD 15 8 R W FAST LOCK_DLY_ONSW _PLLC 0x02AE 19 16 R W ...

Page 126: ..._TIME_PLLD Table 15 125 0x02B8 LOL LOS REFCLK PLLx Reg Address Bit Field Type Setting Name Description 0x02B8 0 R W LOL_LOS_REFCLK _PLLA Set by CBPro 0x02B8 1 R W LOL_LOS_REFCLK _PLLB Set by CBPro 0x02B8 2 R W LOL_LOS_REFCLK _PLLC Set by CBPro 0x02B8 3 R W LOL_LOS_REFCLK _PLLD Set by CBPro Table 15 126 0x02B9 LOL NOSIG TIME PLLx Reg Address Bit Field Type Setting Name Description 0x02B9 0 R W LOL_...

Page 127: ... 0x02BC Reg Address Bit Field Type Setting Name Description 0x02BC 7 6 R W LOS_CMOS_MIN_ PER_EN Set by CBPro Si5397 96 Reference Manual Si5397A B Register Map silabs com Building a more connected world Rev 0 9 127 ...

Page 128: ...Setting Name Description 0x030C 0 S N0_UPDATE Set this bit to latch the N output divider registers into operation Setting this self clearing bit to 1 latches the new N output divider register values into operation A Soft Reset will have the same effect Table 15 131 N0_NUM and N0_DEN Definitions Reg Address Description Size Same as Address 0x030D 0x0312 N1_NUM 44 bit Integer 0x0302 0x0307 0x0313 0x...

Page 129: ...s written all other bits in this register must be written as zeros ClockBuilder Pro handles these updates when changing settings for all portions of the device This control bit is only needed when changing the settings for only a portion of the device while the remaining portion of the device operates undisturbed Si5397 96 Reference Manual Si5397A B Register Map silabs com Building a more connecte...

Page 130: ...x0414 0 must be used to cause all of the BWx_PLLA FAST_BWx_PLLA and BWx_HO_PLLA parameters to take effect Note that individual SOFT_RST_PLLA 0x001C 1 does not update the bandwidth parame ters Table 15 135 0x040E 0x0414 DSPLL A Fast Lock Loop Bandwidth Reg Address Bit Field Type Setting Name Description 0x040E 5 0 R W FAST LOCK_BW0_PLLA Parameters that create the fast lock PLL bandwidth 0x040F 5 0 ...

Page 131: ...E 23 16 R W M_DEN_PLLA 0x041F 31 24 R W M_DEN_PLLA The loop MA divider denominator values are calculated by ClockBuilder Pro for a particular frequency plan and are written into these registers Table 15 138 0x0420 M Divider Update Bit for PLL A Reg Address Bit Field Type Setting Name Description 0x0420 0 S M_UPDATE_PLLA Must write a 1 to this bit to cause PLL A M divider changes to take effect Bit...

Page 132: ...W value is either added to or subtracted from the feedback M divider Numerator such that an FINC will increase the output frequency and an FDEC will decrease the output frequency See also registers 0x0415 0x041F Table 15 142 0x042A DSPLL A Input Clock Select Reg Address Bit Field Type Setting Name Description 0x042A 2 0 R W IN_SEL_PLLA 0 For IN0 1 For IN1 2 For IN2 3 For IN3 4 7 Reserved This is t...

Page 133: ...42E DSPLL A Holdover History Average Length Reg Address Bit Field Type Setting Name Description 0x042E 4 0 R W HOLD_HIST_LEN_ PLLA 5 bit value The holdover logic averages the input frequency over a period of time whose duration is determined by the history average length The average frequency is then used as the holdover frequency See to calculate the window length from the register value time 2LE...

Page 134: ...on Table 15 152 0x0437 DSPLLA Input Alarm Masks Reg Address Bit Field Type Setting Name Description 0x0437 3 0 R W IN_LOS_MSK_PLL A For each clock input LOS alarm 0 To use LOS in the clock selection logic 1 To mask LOS from the clock selection logic 0x0437 7 4 R W IN_OOF_MSK_PLL A For each clock input OOF alarm 0 To use OOF in the clock selection logic 1 To mask OOF from the clock selection logic ...

Page 135: ...2 3 For priority 3 4 For priority 4 5 7 Reserved Table 15 154 0x0439 DSPLL A Clock Inputs 2 and 3 Priority Reg Address Bit Field Type Setting Name Description 0x0439 2 0 R W IN2_PRIORI TY_PLLA The priority for clock input 2 is 0 No priority 1 For priority 1 2 For priority 2 3 For priority 3 4 For priority 4 5 7 Reserved 0x0439 6 4 R W IN3_PRIORI TY_PLLA The priority for clock input 3 is 0 No prior...

Page 136: ...W_COARSE_P M_DLY_PLLA Set by CBPro Table 15 159 0x043F DSPLL A Hold Valid History and Fastlock Status Reg Address Bit Field Type Setting Name Description 0x043F 1 R HOLD_HIST_VAL ID_PLLA Holdover Valid historical frequency data indicator 0 Invalid Holdover History Freerun on input fail or switch 1 Valid Holdover History Holdover on input fail or switch 0x043F 2 R FASTLOCK_STA TUS_PLLA Fastlock eng...

Page 137: ... by CBPro Table 15 163 0x0489 PFD_EN_DELAY_PLLA Reg Address Bit Field Type Setting Name Description 0x0489 7 0 R W PFD_EN_DE LAY_PLLA Set by CBPro 0x048A 12 8 R W PFD_EN_DE LAY_PLLA Table 15 164 0x048B Reg Address Bit Field Type Setting Name Description 0x048B 19 0 R W HSW_MEAS_SET TLE_PLLA Set by CBPro Table 15 165 0x049B HOLDEXIT_BW_SEL0_PLLA Reg Address Bit Field Type Setting Name Description 0...

Page 138: ...HO_PLLA This group of registers determines the DSPLL A bandwidth used when exiting Holdover Mode Clock Builder Pro will then determine the values for each of these registers Either a full device SOFT_RST_ALL 0x001C 0 or the BW_UPDATE_PLLA bit reg 0x0414 0 must be used to cause all of the BWx_PLLA FAST_BWx_PLLA and BWx_HO_PLLA parameters to take effect Note that the individual SOFT_RST_PLLA 0x001C ...

Page 139: ..._MAX_LIM IT_EN_PLLA Set by CBPro 0x04AC 3 R W HOLD_SET TLE_DET_EN_PLL A Set by CBPro 0x04AD 15 0 R W OUT_MAX_LIM IT_LMT_PLLA Set by CBPro 0x04B1 15 0 R W HOLD_SET TLE_TAR GET_PLLA Set by CBPro Si5397 96 Reference Manual Si5397A B Register Map silabs com Building a more connected world Rev 0 9 139 ...

Page 140: ...Wx_PLLB FAST_BWx_PLLB and BWx_HO_PLLB parameters to take effect Note that individual SOFT_RST_PLLB 0x001C 2 does not update the bandwidth parameters Table 15 173 0x050E 0x0514 DSPLL B Fast Lock Loop Bandwidth Reg Address Bit Field Type Setting Name Description 0x050E 5 0 R W FAST LOCK_BW0_PLLB Parameters that create the fast lock PLL bandwidth 0x050F 5 0 R W FAST LOCK_BW1_PLLB 0x0510 5 0 R W FAST ...

Page 141: ...1D 15 8 R W M_DEN_PLLB 0x051E 23 16 R W M_DEN_PLLB 0x051F 31 24 R W M_DEN_PLLB The loop MB divider denominator values are calculated by ClockBuilder Pro for a particular frequency plan and are written into these registers Table 15 176 0x0520 M Divider Update Bit for PLL B Reg Address Bit Field Type Setting Name Description 0x0520 0 S M_UPDATE_PLLB Must write a 1 to this bit to cause PLL B M divide...

Page 142: ...e integer The FSTEPW value is either added to or subtracted from the feedback M divider Numerator such that an FINC will increase the output frequency and an FDEC will decrease the output frequency See also registers 0x0515 0x051F Table 15 180 0x052A DSPLL B Input Clock Select Reg Address Bit Field Type Setting Name Description 0x052A 0 R W IN_SEL_REGCTRL _PLLB 0 Pin Control 1 Register Control 0x0...

Page 143: ... Bit Field Type Setting Name Description 0x052E 4 0 R W HOLD_HIST_LEN_ PLLB 5 bit value The holdover logic averages the input frequency over a period of time whose duration is determined by the history average length The average frequency is then used as the holdover frequency See to calculate the window length from the register value time 2LEN 1 268nsec Table 15 185 0x052F DSPLLB Holdover History...

Page 144: ...le 15 190 0x0537 DSPLLB Input Alarm Masks Reg Address Bit Field Type Setting Name Description 0x0537 3 0 R W IN_LOS_MSK_PLL B For each clock input LOS alarm 0 To use LOS in the clock selection logic 1 To mask LOS from the clock selection logic 0x0537 7 4 R W IN_OOF_MSK_PLL B For each clock input OOF alarm 0 To use OOF in the clock selection logic 1 To mask OOF from the clock selection logic For ea...

Page 145: ...2 3 For priority 3 4 For priority 4 5 7 Reserved Table 15 192 0x0539 DSPLL B Clock Inputs 2 and 3 Priority Reg Address Bit Field Type Setting Name Description 0x0539 2 0 R W IN2_PRIORI TY_PLLB The priority for clock input 2 is 0 No priority 1 For priority 1 2 For priority 2 3 For priority 3 4 For priority 4 5 7 Reserved 0x0539 6 4 R W IN3_PRIORI TY_PLLB The priority for clock input 3 is 0 No prior...

Page 146: ...4 0 R W HSW_COARSE_P M_DLY_PLLB Set by CBPro Table 15 197 0x053F DSPLL B Hold Valid History and Fastlock Status Reg Address Bit Field Type Setting Name Description 0x053F 1 R HOLD_HIST_VAL ID_PLLB Holdover Valid historical frequency data indicator 0 Invalid Holdover History Freerun on input fail or switch 1 Valid Holdover History Holdover on input fail or switch 0x053F 2 R FASTLOCK_STA TUS_PLLB Fa...

Page 147: ... CBPro Table 15 200 0x0588 HSW_FINE_PM_LEN_PLLB Reg Address Bit Field Type Setting Name Description 0x0588 3 0 R W HSW_FINE_PM_LE N_PLLB Set by CBPro Table 15 201 0x0589 PFD_EN_DELAY_PLLB Reg Address Bit Field Type Setting Name Description 0x0589 7 0 R W PFD_EN_DE LAY_PLLB Set by CBPro 0x0589 12 8 R W PFD_EN_DE LAY_PLLB Table 15 202 0x058B Reg Address Bit Field Type Setting Name Description 0x058B...

Page 148: ...E 5 0 R W HOLDEX IT_BW1_PLLB Set by CBPro to set the PLL bandwidth when exiting holdover works with HOLDEXIT_BW_SEL0 and HOLD_BW_SEL1 0x059F 5 0 R W HOLDEX IT_BW2_PLLB 0x05A0 5 0 R W HOLDEX IT_BW3_PLLB 0x05A1 5 0 R W HOLDEX IT_BW4_PLLB 0x05A2 5 0 R W HOLDEX IT_BW5_PLLB This group of registers determines the DSPLL B bandwidth used when exiting Holdover Mode In ClockBuilder Pro it is selectable from...

Page 149: ...quency ramping is used for holdover exit Set by CBPro 0x05A6 3 R W RAMP_SWITCH_E N_PLLB 1 enable frequency ramping on holdover exit Table 15 208 0x05AC 0x05B2 Reg Address Bit Field Type Setting Name Description 0x05AC 0 R W OUT_MAX_LIM IT_EN_PLLB Set by CBPro 0x05AC 3 R W HOLD_SET TLE_DET_EN_PLL B Set by CBPro 0x05AD 15 0 R W OUT_MAX_LIM IT_LMT_PLLB Set by CBPro 0x05B1 15 0 R W HOLD_SET TLE_TAR GE...

Page 150: ...Wx_PLLC FAST_BWx_PLLC and BWx_HO_PLLC parameters to take effect Note that individual SOFT_RST_PLLC 0x001C 3 does not update the bandwidth parameters Table 15 211 0x060E 0x0614 DSPLL C Fast Lock Loop Bandwidth Reg Address Bit Field Type Setting Name Description 0x060E 5 0 R W FAST LOCK_BW0_PLLC Parameters that create the fast lock PLL bandwidth 0x060F 5 0 R W FAST LOCK_BW1_PLLC 0x0610 5 0 R W FAST ...

Page 151: ...61E 23 16 R W M_DEN_PLLC 0x061F 31 24 R W M_DEN_PLLC The loop MC divider denominator values are calculated by ClockBuilder Pro for a particular frequency plan and are written into these registers Table 15 214 0x0620 M Divider Update Bit for PLL C Reg Address Bit Field Type Setting Name Description 0x0620 0 S M_UPDATE_PLLC Must write a 1 to this bit to cause PLL C M divider changes to take effect B...

Page 152: ...eger The FSTEPW value is either added to or subtracted from the feedback M divider Numerator such that an FINC will increase the output frequency and an FDEC will decrease the output frequency See also Registers 0x0615 0x061F Table 15 218 0x062A DSPLL C Input Clock Select Reg Address Bit Field Type Setting Name Description 0x062A 2 0 R W IN_SEL_PLLC 0 For IN0 1 For IN1 2 For IN2 3 For IN3 4 7 Rese...

Page 153: ...over logic averages the input frequency over a period of time whose duration is determined by the history average length The average frequency is then used as the holdover frequency See to calculate the window length from the register value time 2LEN 1 268nsec Table 15 223 0x062F DSPLLC Holdover History Delay Reg Address Bit Field Type Setting Name Description 0x062F 4 0 R W HOLD_HIST_DE LAY_PLLC ...

Page 154: ...Table 15 228 0x0637 DSPLLC Input Alarm Masks Reg Address Bit Field Type Setting Name Description 0x0637 3 0 R W IN_LOS_MSK_PLL C For each clock input LOS alarm 0 To use LOS in the clock selection logic 1 To mask LOS from the clock selection logic 0x0637 7 4 R W IN_OOF_MSK_PLL C For each clock input OOF alarm 0 To use OOF in the clock selection logic 1 To mask OOF from the clock selection logic For...

Page 155: ...2 3 For priority 3 4 For priority 4 5 7 Reserved Table 15 230 0x0639 DSPLL C Clock Inputs 2 and 3 Priority Reg Address Bit Field Type Setting Name Description 0x0639 2 0 R W IN2_PRIORI TY_PLLC The priority for clock input 2 is 0 No priority 1 For priority 1 2 For priority 2 3 For priority 3 4 For priority 4 5 7 Reserved 0x0639 6 4 R W IN3_PRIORI TY_PLLC The priority for clock input 3 is 0 No prior...

Page 156: ...R W HSW_COARSE_P M_DLY_PLLC Set by CBPro Table 15 235 0x063F DSPLL C Hold Valid History and Fastlock Status Reg Address Bit Field Type Setting Name Description 0x063F 1 R HOLD_HIST_VAL ID_PLLC Holdover Valid historical frequency data indicator 0 Invalid Holdover History Freerun on input fail or switch 1 Valid Holdover History Holdover on input fail or switch 0x063F 2 R FASTLOCK_STA TUS_PLLC Fastlo...

Page 157: ...LLC Set by CBPro Table 15 239 0x0689 PFD_EN_DELAY_PLLC Reg Address Bit Field Type Setting Name Description 0x0689 7 0 R W PFD_EN_DE LAY_PLLC Set byCBPro 0x0689 12 8 R W PFD_EN_DE LAY_PLLC Table 15 240 0x068B Reg Address Bit Field Type Setting Name Description 0x068B 19 0 R W HSW_MEAS_SET TLE_PLLC Set by CBPro Table 15 241 0x069B HOLDEXIT_BW_SEL0_PLLC Reg Address Bit Field Type Setting Name Descrip...

Page 158: ...T_BW2_PLLC 0x06A0 5 0 R W HOLDEX IT_BW3_PLLC 0x06A1 5 0 R W HOLDEX IT_BW4_PLLC 0x06A2 5 0 R W HOLDEX IT_BW5_PLLC This group of registers determines the DSPLL C bandwidth used when exiting Holdover Mode Clock Builder Pro will then determine the values for each of these registers Either a full device SOFT_RST_ALL 0x001C 0 or the BW_UPDATE_PLLC bit reg 0x0614 0 must be used to cause all of the BWx_PL...

Page 159: ...C 0x06B2 Reg Address Bit Field Type Setting Name Description 0x06AC 0 R W OUT_MAX_LIM IT_EN_PLLC Set by CBPro 0x06AC 3 R W HOLD_SET TLE_DET_EN_PLL C Set by CBPro 0x06AD 15 0 R W OUT_MAX_LIM IT_LMT_PLLC Set by CBPro 0x06B1 15 0 R W HOLD_SET TLE_TAR GET_PLLC Set by CBPro Si5397 96 Reference Manual Si5397A B Register Map silabs com Building a more connected world Rev 0 9 159 ...

Page 160: ... 5 0 R W BW4_PLLD 0x070E 5 0 R W BW5_PLLD This group of registers determines the DSPLL D loop bandwidth Clock Builder Pro will then determine the values for each of these registers Either a full device SOFT_RST_ALL 0x001C 0 or the BW_UPDATE_PLLD bit reg 0x0715 0 must be used to cause all of the BWx_PLLD FAST_BWx_PLLD and BWx_HO_PLLD parameters to take effect Note that individual SOFT_RST_PLLD 0x00...

Page 161: ...or values are calculated by ClockBuilder Pro for a particular frequency plan and are written into these registers Table 15 251 0x071D 0x0720 MD Divider Denominator for DSPLL D Reg Address Bit Field Type Setting Name Description 0x071D 7 0 R W M_DEN_PLLD 32 bit number 0x071E 15 8 R W M_DEN_PLLD 0x071F 23 16 R W M_DEN_PLLD 0x0720 31 24 R W M_DEN_PLLD The loop MD divider denominator values are calcul...

Page 162: ...number 0x0725 15 8 R W M_FSTEPW_PLLD 0x0726 23 16 R W M_FSTEPW_PLLD 0x0727 31 24 R W M_FSTEPW_PLLD 0x0728 39 32 R W M_FSTEPW_PLLD 0x0729 47 40 R W M_FSTEPW_PLLD 0x072A 55 48 R W M_FSTEPW_PLLD The frequency step word FSTEPW for the feedback M divider of DSPLL D is always a positive integer The FSTEPW value is either added to or subtracted from the feedback M divider Numerator such that an FINC will...

Page 163: ...0x072E 1 R W HOLD_RAMP BYP_NOH IST_PLLD Set by CBPro Table 15 260 0x072F DSPLL D Holdover History Average Length Reg Address Bit Field Type Setting Name Description 0x072F 4 0 R W HOLD_HIST_LEN_ PLLD 5 bit value The holdover logic averages the input frequency over a period of time whose duration is determined by the history average length The average frequency is then used as the holdover frequenc...

Page 164: ... Type Setting Name Description 0x0737 1 0 R W CLK_SWITCH_MO DE_PLLD Clock Selection Mode 0 Manual 1 Automatic non revertive 2 Automatic revertive 3 Reserved 0x0737 2 R W HSW_EN_PLLD 0 Glitchless switching mode phase buildout turned off 1 Hitless switching mode phase buildout turned on Table 15 266 0x0738 DSPLLD Input Alarm Masks Reg Address Bit Field Type Setting Name Description 0x0738 3 0 R W IN...

Page 165: ...pe Setting Name Description 0x0739 2 0 R W IN0_PRIORI TY_PLLD The priority for clock input 0 is 0 No priority 1 For priority 1 2 For priority 2 3 For priority 3 4 For priority 4 5 7 Reserved 0x0739 6 4 R W IN1_PRIORI TY_PLLD The priority for clock input 1 is 0 No priority 1 For priority 1 2 For priority 2 3 For priority 3 4 For priority 4 5 7 Reserved Table 15 268 0x073A DSPLL D Clock Inputs 2 and...

Page 166: ...iption 0x073C 7 0 R W HSW_PHMEAS_TH R_PLLD 10 bit value Set by CBPro 0x073D 9 8 R W HSW_PHMEAS_TH R_PLLD Table 15 271 0x073E Reg Address Bit Field Type Setting Name Description 0x073E 4 0 R W HSW_COARSE_P M_LEN_PLLD Set by CBPro Table 15 272 0x073F Reg Address Bit Field Type Setting Name Description 0x073F 4 0 R W HSW_COARSE_P M_DLY_PLLD Set by CBPro Table 15 273 0x0740 DSPLL D Hold Valid History ...

Page 167: ...y CBPro 0x0744 15 8 R W FINE_ADJ_OVR_P LLD Set by CBPro 0x0745 17 16 R W FINE_ADJ_OVR_P LLD Set by CBPro Table 15 275 0x0746 Reg Address Bit Field Type Setting Name Description 0x0746 1 R W FORCE_FINE_ADJ _PLLD Set by CBPro Table 15 276 0x0789 0x078A Reg Address Bit Field Type Setting Name Description 0x0789 7 0 R W PFD_EN_DE LAY_PLLD Set by CBPro 0x078A 12 8 R W PFD_EN_DE LAY_PLLD Set by CBPro Ta...

Page 168: ...LD 0x079F 5 0 R W HOLDEX IT_BW2_PLLD 0x07A0 5 0 R W HOLDEX IT_BW3_PLLD 0x07A1 5 0 R W HOLDEX IT_BW4_PLLD 0x07A2 5 0 R W HOLDEX IT_BW5_PLLD This group of registers determines the DSPLL D bandwidth used when exiting Holdover Mode Clock Builder Pro will then determine the values for each of these registers Either a full device SOFT_RST_ALL 0x001C 0 or the BW_UPDATE_PLLD bit reg 0x0715 0 must be used ...

Page 169: ...C 0x07B2 Reg Address Bit Field Type Setting Name Description 0x07AC 0 R W OUT_MAX_LIM IT_EN_PLLD Set by CBPro 0x07AC 3 R W HOLD_SET TLE_DET_EN_PLL D Set by CBPro 0x07AD 15 0 R W OUT_MAX_LIM IT_LMT_PLLD Set by CBPro 0x07B1 15 0 R W HOLD_SET TLE_TAR GET_PLLD Set by CBPro Si5397 96 Reference Manual Si5397A B Register Map silabs com Building a more connected world Rev 0 9 169 ...

Page 170: ...e are operating with the optimum signal thresholds Table 15 286 0x0949 Clock Input Control and Configuration Reg Address Bit Field Type Setting Name Description 0x0949 3 0 R W IN_EN 0 Disable and Powerdown Input Buffer 1 Enable Input Buffer for IN3 IN0 0x0949 7 4 R W IN_PULSED_CMO S_EN 0 Standard Input Format 1 Pulsed CMOS Input Format for IN3 IN0 See for more information When a clock is disabled ...

Page 171: ...mmended if changing settings during operation 1 Integer only division best phase noise Recommen ded for Integer N values Note that a device Soft Reset 0x001C 0 1 must be is sued after changing the settings in this register ClockBuilder Pro handles these bits when changing settings for all portions of the device This control bit is only needed when changing the settings for only a portion of the de...

Page 172: ...DIS_ PLLA Clock disable for the fractional divide of the M divider in PLLA Must be set to a 0 if this M divider has a fraction al value 0 Enable the clock to the fractional divide part of the M divider 1 Disable the clock to the fractional divide part of the M divider 0x0B44 5 R W FRACN_CLK_DIS_ PLLB Clock disable for the fractional divide of the M divider in PLLB Must be set to a 0 if this M divi...

Page 173: ...the respective inputs ClockBuilder Pro handles these bits when changing settings for all portions of the device This control bit is only needed when changing the settings for only a portion of the device while the remaining portion of the device operates undisturbed Table 15 298 0x0B47 Reg Address Bit Field Type Name Description 0x0B47 4 0 R W OOF_CLK_DIS Set by CBPro Table 15 299 0x0B48 Reg Addre...

Page 174: ...e operates undisturbed Table 15 301 0x0B4E Reserved Control Reg Address Bit Field Type Name Description 0x0B4E 7 0 R W RESERVED Internal use for initilization See CBPro Table 15 302 0x0B57 VCO_RESET_CALCODE Reg Address Bit Field Type Name Description 0x0B57 7 0 R W VCO_RESET_CAL CODE 0x0B58 11 8 R W VCO_RESET_CAL CODE Si5397 96 Reference Manual Si5397A B Register Map silabs com Building a more con...

Page 175: ...Bit Field Type Name Description 0x0C06 7 0 R W IN_CLK_VAL_TIME_P LLA Set by CBPro Table 15 307 0x0C07 Reg Address Bit Field Type Name Description 0x0C07 0 R W IN_CLK_VAL_EN _PLLB Set by CBPro Table 15 308 0x0C08 Reg Address Bit Field Type Name Description 0x0C08 7 0 R W IN_CLK_VAL_TIME_P LLB Set by CBPro Table 15 309 0x0C09 Reg Address Bit Field Type Name Description 0x0C09 0 R W IN_CLK_VAL_EN _PL...

Page 176: ... 0x0C0B 0 R W IN_CLK_VAL_EN _PLLD Set by CBPro Table 15 312 0x0C0C Reg Address Bit Field Type Name Description 0x0C0C 7 0 R W IN_CLK_VAL_TIME_P LLD Set by CBPro Si5397 96 Reference Manual Si5397A B Register Map silabs com Building a more connected world Rev 0 9 176 ...

Page 177: ...ion 0x0002 7 0 R PN_BASE 0x47 Four digit base part number one nibble per digit Example Si5397A A GM The base part num ber OPN is 5397 which is stored in this regis ter 0x0003 15 8 R PN_BASE 0x53 Table 16 4 0x0004 Device Grade Reg Address Bit Field Type Setting Name Description 0x0004 7 0 R GRADE One ASCII character indicating the device speed synthesis mode 0 A 1 B 2 C 3 D 10 J 11 K 12 L 13 M Refe...

Page 178: ...n and all other operating characteristics defined by the user s ClockBuilder Pro project file Si5397C A GM Applies to a base or blank OPN device Base devices are factory pre programmed to a specific base part type e g Si5397 but exclude any user defined frequency plan or other user defined operating characteristics selected in ClockBuilder Pro Table 16 8 0x000B I2C Address Reg Address Bit Field Ty...

Page 179: ...g Name Description 0x000E 3 0 R LOL_PLL D A 1 if the DSPLL is out of lock 0x000E 7 4 R HOLD_PLL D A 1 if the DSPLL is in holdover or free run DSPLL_A corresponds to bit 0 4 DSPLL_B corresponds to bit 1 5 DSPLL_C corresponds to bit 2 6 DSPLL_D corresponds to bit 3 7 Table 16 12 0x000F INCAL Status Reg Address Bit Field Type Setting Name Description 0x000F 7 4 R CAL_PLL D A 1 if the DSPLL internal c...

Page 180: ...LOS_FLG 0x0012 3 OOF_FLG 0x0012 7 Table 16 15 0x0013 Holdover and LOL Flags Reg Address Bit Field Type Setting Name Description 0x0013 3 0 R W LOL_FLG_PLL D A 1 if the DSPLL was unlocked 0x0013 7 4 R W HOLD_FLG_PLL D A 1 if the DSPLL was in holdover or freerun Sticky flag versions of address 0x000E DSPLL_A corresponds to bit 0 4 DSPLL_B corresponds to bit 1 5 DSPLL_C corresponds to bit 2 6 DSPLL_D...

Page 181: ...Input 0 IN0 corresponds to LOS_IN_INTR_MSK 0x0018 0 OOF_IN_INTR_MSK 0x0018 4 Input 1 IN1 corresponds to LOS_IN_INTR_MSK 0x0018 1 OOF_IN_INTR_MSK 0x0018 5 Input 2 IN2 corresponds to LOS_IN_INTR_MSK 0x0018 2 OOF_IN_INTR_MSK 0x0018 6 Input 3 IN3 corresponds to LOS_IN_INTR_MSK 0x0018 3 OOF_IN_INTR_MSK 0x0018 7 These are the interrupt mask bits for the OOF and LOS flags in register 0x0012 If a mask bit...

Page 182: ...which means self clearing Unlike SOFT_RST_ALL the SOFT_RST_PLLx bits do not update the loop BW values If these have changed the update can be done by writing to BW_UPDATE_PLLA BW_UPDATE_PLLB BW_UPDATE_PLLC and BW_UPDATE_PLLD at addresses 0x0414 0x514 0x0614 and 0x0715 Table 16 23 0x001D FINC FDEC Reg Address Bit Field Type Setting Name Description 0x001D 0 S FINC 0 No effect 1 A rising edge will c...

Page 183: ... D M divider By default ClockBuilder Pro sets OE0 controlling all outputs and OE1 unused OUTALL_DISABLE_LOW 0x0102 0 must be high ena bled to observe the effects of OE0 and OE1 Note that the OE0 and OE1 register bits active high have inverted logic sense from the pins active low Table 16 26 0x002B SPI 3 vs 4 Wire Reg Address Bit Field Type Setting Name Description 0x002B 3 R W SPI_3WIRE 0 For 4 wi...

Page 184: ...or Input 0 given a particular frequency plan Table 16 30 0x0030 0x0031 LOS1 Trigger Threshold Reg Address Bit Field Type Setting Name Description 0x0030 7 0 R W LOS1_TRG_THR 16 bit Threshold Value 0x0031 15 8 R W LOS1_TRG_THR ClockBuilder Pro calculates the correct LOS register threshold trigger value for Input 1 given a particular frequency plan Table 16 31 0x0032 0x0033 LOS2 Trigger Threshold Re...

Page 185: ...escription 0x003A 7 0 R W LOS2_CLR_THR 16 bit Threshold Value 0x003B 15 8 R W LOS2_CLR_THR ClockBuilder Pro calculates the correct LOS register clear threshold value for Input 2 given a particular frequency plan Table 16 36 0x003C 0x003D LOS3 Clear Threshold Reg Address Bit Field Type Setting Name Description 0x003C 7 0 R W LOS3_CLR_THR 16 bit Threshold Value 0x003D 15 8 R W LOS3_CLR_THR ClockBuil...

Page 186: ...R W OOF0_SET_THR OOF Set Threshold Range is up to 500 ppm in steps of 1 16 ppm 0x0047 7 0 R W OOF1_SET_THR OOF Set Threshold Range is up to 500 ppm in steps of 1 16 ppm 0x0048 7 0 R W OOF2_SET_THR OOF Set Threshold Range is up to 500 ppm in steps of 1 16 ppm 0x0049 7 0 R W OOF3_SET_THR OOF Set Threshold Range is up to 500 ppm in steps of 1 16 ppm Table 16 42 0x004A 0x004D Out of Frequency Clear Th...

Page 187: ...2 IN1 and IN0 when the fast control is enabled The value in each of the register is 1 value x 1000 ppm ClockBuilder Pro is used to determine the values for these registers Table 16 46 0x0055 0x0058 Fast Out of Frequency Clear Threshold Reg Address Bit Field Type Setting Name Description 0x0055 3 0 R W FAST_OOF0_CLR_ THR 1 value x 1000 ppm 0x0056 3 0 R W FAST_OOF1_CLR_ THR 1 value x 1000 ppm 0x0057...

Page 188: ...ld Type Setting Name Description 0x005E 7 0 R W OOF1_RATIO_REF Values calculated by CBPro 0x005F 15 8 R W OOF1_RATIO_REF 0x0060 23 16 R W OOF1_RATIO_REF 0x0061 25 24 R W OOF1_RATIO_REF Table 16 50 0x0062 0x0065 OOF2 Ratio for Reference Reg Address Bit Field Type Setting Name Description 0x0062 7 0 R W OOF2_RATIO_REF Values calculated by CBPro 0x0063 15 8 R W OOF2_RATIO_REF 0x0064 23 16 R W OOF2_RA...

Page 189: ... W LOL_FST_DET WIN_SEL_PLLC 0x0094 7 4 R W LOL_FST_DET WIN_SEL_PLLD Table 16 54 0x0095 Fast LOL Detection Value Reg Address Bit Field Type Setting Name Description 0x0095 1 0 R W LOL_FST_VAL WIN_SEL_PLLA Values calculated by CBPro 0x0095 3 2 R W LOL_FST_VAL WIN_SEL_PLLB 0x0095 5 4 R W LOL_FST_VAL WIN_SEL_PLLC 0x0095 7 6 R W LOL_FST_VAL WIN_SEL_PLLD Table 16 55 0x0096 0x0097 Fast LOL Set Threshold ...

Page 190: ... 0 To disable LOL 1 To enable LOL 0x009A 1 LOL_SLOW_EN_P LLB 0 To disable LOL 1 To enable LOL 0x009A 2 LOL_SLOW_EN_P LLC 0 To disable LOL 1 To enable LOL 0x009A 3 LOL_SLOW_EN_P LLD 0 To disable LOL 1 To enable LOL Table 16 58 0x009B 0x009C Slow LOL Detection Value Reg Address Bit Field Type Setting Name Description 0x009B 3 0 R W LOL_SLW_DET WIN_SEL_PLLA Values calculated by CBPro 0x009B 7 4 R W L...

Page 191: ...09F 3 0 R W LOL_SLW_SET_TH R_PLLC Configures the loss of lock set thresholds See list be low for selectable values 0x009F 7 4 R W LOL_SLW_SET_TH R_PLLD Configures the loss of lock set thresholds See list be low for selectable values The following are the LOL_SLW_SET_THR_PLLx thresholds for the value that is placed in the four bits for DSPLLs 0 0 1 ppm 1 0 3 ppm 2 1 ppm 3 3 ppm 4 10 ppm 5 30 ppm 6 ...

Page 192: ... ppm 10 10000 ppm 11 15 Reserved Table 16 64 0x00A2 LOL Timer Enable Reg Address Bit Field Type Setting Name Description 0x00A2 0 1 2 3 R W LOL_TIM ER_EN_PLLA LOL_TIM ER_EN_PLLB LOL_TIM ER_EN_PLLC LOL_TIM ER_EN_PLLD Enable Delay for LOL Clear 0 Disable Delay for LOL Clear 1 Enable Delay for LOL Clear Table 16 65 0x00A4 0x00A7 LOL Clear Delay DSPLL A Reg Address Bit Field Type Setting Name Descript...

Page 193: ...AY_DIV256_PLLC 0x00B1 28 24 R W LOL_CLR_DE LAY_DIV256_PLLC Table 16 68 0x00B3 0x00B6 LOL Clear Delay DSPLL D Reg Address Bit Field Type Setting Name Description 0x00B3 7 0 R W LOL_CLR_DE LAY_DIV256_PLLD 29 bit value Sets the clear timer 0x00AA 15 8 R W LOL_CLR_DLY for LOL CBPro sets this value 0x00B4 15 8 R W LOL_CLR_DE LAY_DIV256_PLLD 0x00B5 23 16 R W LOL_CLR_DE LAY_DIV256_PLLD 0x00B6 28 24 R W L...

Page 194: ...dress Bit Field Type Setting Name Description 0x00E6 7 0 R W FASTLOCK_EX TEND_PLLA 29 bit value Set by CBPro to minimize the phase tran sients when switching the PLL bandwidth See FAST LOCK_EXTEND_SCL_PLLx 0x00E7 15 8 R W FASTLOCK_EX TEND_PLLA 0x00E8 23 16 R W FASTLOCK_EX TEND_PLLA 0x00E9 28 24 R W FASTLOCK_EX TEND_PLLA Table 16 74 0x00EA 0x00ED FASTLOCK_EXTEND_PLLB Reg Address Bit Field Type Sett...

Page 195: ...mize the phase tran sients when switching the PLL bandwidth See FAST LOCK_EXTEND_SCL_PLLx 0x00F3 15 8 R W FASTLOCK_EX TEND_PLLD 0x00F4 23 16 R W FASTLOCK_EX TEND_PLLD 0x00F5 28 24 R W FASTLOCK_EX TEND_PLLD Table 16 77 0x00F6 Reg Address Bit Field Type Name Description 0x00F6 0 R REG_0XF7_INT R Set by CBPro 0x00F6 1 R REG_0XF8_INT R Set by CBPro 0x00F6 2 R REG_0XF9_INT R Set by CBPro Table 16 78 0x...

Page 196: ...Name Description 0x00FE 7 0 R DEVICE_READY Ready Only byte to indicate device is ready When read data is 0x0F one can safely read write registers This register is repeated on every page so that a page write is not ever required to read the DEVICE_READY sta tus WARNING Any attempt to read or write any register other than DEVICE_READY before DEVICE_READY reads as 0x0F may corrupt the NVM programming...

Page 197: ...108 0x011C 0x0126 0x012B 1 R W OUT0_OE OUT1_OE OUT2_OE OUT3_OE 0 To disable the output 1 To enable the output 0x0108 0x011C 0x0126 0x012B 2 R W OUT0_RDIV_ FORCE OUT1_RDIV_ FORCE OUT2_RDIV_ FORCE OUT3_RDIV_ FORCE Force Rx output divider divide by 2 0 Rx_REG sets divide value default 1 Divide value forced to divide by 2 The output drivers are all identical See Table 16 84 0x0109 0x011D 0x0127 0x012C...

Page 198: ...ion 0x010A 0x011E 0x0128 0x012D 3 0 R W OUT0_CM OUT1_CM OUT2_CM OUT3_CM OUTx common mode voltage selection This field only applies when OUTx_FORMAT 1 or 2 See 0x010A 0x011E 0x0128 0x012D 6 4 R W OUT0_AMPL OUT1_AMPL OUT2_AMPL OUT3_AMPL OUTx common mode voltage selection This field only applies when OUTx_FORMAT 1 or 2 See ClockBuilder Pro is used to select the correct settings for this register The ...

Page 199: ...16 0x011B 0x0120 0x012A 0x012F 0x0134 0x0139 Output Disable Source DSPLL Reg Address Bit Field Type Setting Name Description 0x010C 0x0120 0x012A 0x012F 2 0 R W OUT0_DIS_SRC OUT1_DIS_SRC OUT2_DIS_SRC OUT3_DIS_SRC Output driver 0 input mux select This selects the source of the output clock 0 DSPLL A squelches output 1 DSPLL B squelches output 2 DSPLL C squelches output 3 DSPLL D squelches output 5 ...

Page 200: ...by CBPro Table 16 89 0x0142 Output Disable Loss of Lock PLL Reg Address Bit Field Type Setting Name Description 0x0142 3 0 R W OUT_DIS_MSK_LO L_PLL D A 0 LOL will disable all connected outputs 1 LOL does not disable any outputs 0x0142 7 4 R W OUT_DIS_MSK_H OLD_PLL D A Set by CBPro Bit 0 LOL_DSPLL_A mask Bit 1 LOL_DSPLL_B mask Bit 2 LOL_DSPLL_C mask Bit 3 LOL_DSPLL_D mask Si5397 96 Reference Manual...

Page 201: ...ers Note that changing these registers during operation may cause indefinite loss of lock unless the guidelines in are followed Table 16 92 0x020E 0x0211 P0 Divider Denominator Reg Address Bit Field Type Setting Name Description 0x020E 7 0 R W P0_DEN 32 bit Integer Number 0x020F 15 8 R W P0_DEN 0x0210 23 16 R W P0_DEN 0x0211 31 24 R W P0_DEN The P1 P2 and P3 divider numerator and denominator follo...

Page 202: ..._PLLB etc as these do not update the Px_NUM or Px_DEN values Table 16 95 0x0231 P0 Factional Division Enable Reg Address Bit Field Type Setting Name Description 0x0231 3 0 R W P0_FRACN_MODE P0 IN0 input divider fractional mode Must be set to 0xB for proper operation 0x0231 4 R W P0_FRAC_EN P0 IN0 input divider fractional enable 0 Integer only division 1 Fractional or Integer division Table 16 96 0...

Page 203: ...Note that changing this register during operation may cause indefinite loss of lock unless the guidelines in are followed Table 16 100 0x023B 0x023E MXAXB Divider Denominator Reg Address Bit Field Type Setting Name Description 0x023B 7 0 R W MXAXB_DEN 32 bit Integer Number 0x023C 15 8 R W MXAXB_DEN 0x023D 23 16 R W MXAXB_DEN 0x023E 31 24 R W MXAXB_DEN The M divider numerator and denominator are se...

Page 204: ...Number 0x024A 0x024C 0x025F 0x0261 R3_REG 24 bit Integer Number 0x024A 0x024C Table 16 104 0x026B 0x0272 Design Identifier Reg Address Bit Field Type Setting Name Description 0x026B 7 0 R W DESIGN_ID0 ASCII encoded string defined by ClockBuilder Pro user with user defined space or null padding of unused char acters A user will normally include a configuration ID revision ID For example ULT 1A with...

Page 205: ...c base part type e g Si5397 but exclude any user defined frequency plan or other user defined operating characteristics selected in ClockBuilder Pro Table 16 106 0x027D Reg Address Bit Field Type Setting Name Description 0x027D 7 0 R W OPN_REVISION Table 16 107 0x027E Reg Address Bit Field Type Setting Name Description 0x027E 7 0 R W BASELINE_ID Table 16 108 0x028A 0x028D Reg Address Bit Field Typ...

Page 206: ...s Bit Field Type Setting Name Description 0x0292 3 0 R W OOF_STOP_ON_L OS Set by CBPro 0x0293 3 0 R W OOF_CLEAR_ON_ LOS Set by CBPro Table 16 111 0x0294 0x0295 FASTLOCK EXTEND SCL PLLx Reg Address Bit Field Type Setting Name Description 0x0294 3 0 R W FASTLOCK_EX TEND_SCL_PLLA Scales LOLB_INT_TIMER_DIV256 Set by CBPro 0x0294 7 4 R W FASTLOCK_EX TEND_SCL_PLLB 0x0295 3 0 R W FASTLOCK_EX TEND_SCL_PLL...

Page 207: ...Setting Name Description 0x0299 0 R W FAST LOCK_DLY_ON LOL_EN_PLLA Set by CBPro 0x0299 1 R W FAST LOCK_DLY_ON LOL_EN_PLLB 0x0299 2 R W FAST LOCK_DLY_ON LOL_EN_PLLC 0x0299 3 R W FAST LOCK_DLY_ON LOL_EN_PLLD Table 16 115 0x029A 0x29C FASTLOCK_DLY_ONLOL_PLLA Reg Address Bit Field Type Setting Name Description 0x029A 7 0 R W FAST LOCK_DLY_ON LOL_PLLA Set by CBPro 0x029B 15 8 R W FAST LOCK_DLY_ON LOL_P...

Page 208: ...Type Setting Name Description 0x02A0 7 0 R W FAST LOCK_DLY_ON LOL_PLLC Set by CBPro 0x02A1 15 8 R W FAST LOCK_DLY_ON LOL_PLLC 0x02A2 19 16 R W FAST LOCK_DLY_ON LOL_PLLC Table 16 118 0x02A3 0x02A5 FASTLOCK_DLY_ONLOL_PLLD Reg Address Bit Field Type Setting Name Description 0x02A3 7 0 R W FAST LOCK_DLY_ON LOL_PLLD Set by CBPro 0x02A4 15 8 R W FAST LOCK_DLY_ON LOL_PLLD 0x02A5 19 16 R W FAST LOCK_DLY_O...

Page 209: ...Setting Name Description 0x02A9 7 0 R W FAST LOCK_DLY_ONSW _PLLB 20 bit value Set by CBPro 0x02AA 15 8 R W FAST LOCK_DLY_ONSW _PLLB 0x02AB 19 16 R W FAST LOCK_DLY_ONSW _PLLB Table 16 121 0x02AC 0x02AE FASTLOCK_DLY_ONSW_PLLC Reg Address Bit Field Type Setting Name Description 0x02AC 7 0 R W FAST LOCK_DLY_ONSW _PLLC 20 bit value Set by CBPro 0x02AD 15 8 R W FAST LOCK_DLY_ONSW _PLLC 0x02AE 19 16 R W ...

Page 210: ..._TIME_PLLD Table 16 124 0x02B8 LOL LOS REFCLK PLLx Reg Address Bit Field Type Setting Name Description 0x02B8 0 R W LOL_LOS_REFCLK _PLLA Set by CBPro 0x02B8 1 R W LOL_LOS_REFCLK _PLLB Set by CBPro 0x02B8 2 R W LOL_LOS_REFCLK _PLLC Set by CBPro 0x02B8 3 R W LOL_LOS_REFCLK _PLLD Set by CBPro Table 16 125 0x02B9 LOL NOSIG TIME PLLx Reg Address Bit Field Type Setting Name Description 0x02B9 0 R W LOL_...

Page 211: ... 0x02BC Reg Address Bit Field Type Setting Name Description 0x02BC 7 6 R W LOS_CMOS_MIN_ PER_EN Set by CBPro Si5397 96 Reference Manual Si5397C D Register Map silabs com Building a more connected world Rev 0 9 211 ...

Page 212: ...Setting Name Description 0x030C 0 S N0_UPDATE Set this bit to latch the N output divider registers into operation Setting this self clearing bit to 1 latches the new N output divider register values into operation A Soft Reset will have the same effect Table 16 130 N0_NUM and N0_DEN Definitions Reg Address Description Size Same as Address 0x030D 0x0312 N1_NUM 44 bit Integer 0x0302 0x0307 0x0313 0x...

Page 213: ...s written all other bits in this register must be written as zeros ClockBuilder Pro handles these updates when changing settings for all portions of the device This control bit is only needed when changing the settings for only a portion of the device while the remaining portion of the device operates undisturbed Si5397 96 Reference Manual Si5397C D Register Map silabs com Building a more connecte...

Page 214: ...x0414 0 must be used to cause all of the BWx_PLLA FAST_BWx_PLLA and BWx_HO_PLLA parameters to take effect Note that individual SOFT_RST_PLLA 0x001C 1 does not update the bandwidth parame ters Table 16 134 0x040E 0x0414 DSPLL A Fast Lock Loop Bandwidth Reg Address Bit Field Type Setting Name Description 0x040E 5 0 R W FAST LOCK_BW0_PLLA Parameters that create the fast lock PLL bandwidth 0x040F 5 0 ...

Page 215: ...E 23 16 R W M_DEN_PLLA 0x041F 31 24 R W M_DEN_PLLA The loop MA divider denominator values are calculated by ClockBuilder Pro for a particular frequency plan and are written into these registers Table 16 137 0x0420 M Divider Update Bit for PLL A Reg Address Bit Field Type Setting Name Description 0x0420 0 S M_UPDATE_PLLA Must write a 1 to this bit to cause PLL A M divider changes to take effect Bit...

Page 216: ...W value is either added to or subtracted from the feedback M divider Numerator such that an FINC will increase the output frequency and an FDEC will decrease the output frequency See also registers 0x0415 0x041F Table 16 141 0x042A DSPLL A Input Clock Select Reg Address Bit Field Type Setting Name Description 0x042A 2 0 R W IN_SEL_PLLA 0 For IN0 1 For IN1 2 For IN2 3 For IN3 4 7 Reserved This is t...

Page 217: ...42E DSPLL A Holdover History Average Length Reg Address Bit Field Type Setting Name Description 0x042E 4 0 R W HOLD_HIST_LEN_ PLLA 5 bit value The holdover logic averages the input frequency over a period of time whose duration is determined by the history average length The average frequency is then used as the holdover frequency See to calculate the window length from the register value time 2LE...

Page 218: ...on Table 16 151 0x0437 DSPLLA Input Alarm Masks Reg Address Bit Field Type Setting Name Description 0x0437 3 0 R W IN_LOS_MSK_PLL A For each clock input LOS alarm 0 To use LOS in the clock selection logic 1 To mask LOS from the clock selection logic 0x0437 7 4 R W IN_OOF_MSK_PLL A For each clock input OOF alarm 0 To use OOF in the clock selection logic 1 To mask OOF from the clock selection logic ...

Page 219: ...2 3 For priority 3 4 For priority 4 5 7 Reserved Table 16 153 0x0439 DSPLL A Clock Inputs 2 and 3 Priority Reg Address Bit Field Type Setting Name Description 0x0439 2 0 R W IN2_PRIORI TY_PLLA The priority for clock input 2 is 0 No priority 1 For priority 1 2 For priority 2 3 For priority 3 4 For priority 4 5 7 Reserved 0x0439 6 4 R W IN3_PRIORI TY_PLLA The priority for clock input 3 is 0 No prior...

Page 220: ...W_COARSE_P M_DLY_PLLA Set by CBPro Table 16 158 0x043F DSPLL A Hold Valid History and Fastlock Status Reg Address Bit Field Type Setting Name Description 0x043F 1 R HOLD_HIST_VAL ID_PLLA Holdover Valid historical frequency data indicator 0 Invalid Holdover History Freerun on input fail or switch 1 Valid Holdover History Holdover on input fail or switch 0x043F 2 R FASTLOCK_STA TUS_PLLA Fastlock eng...

Page 221: ... by CBPro Table 16 162 0x0489 PFD_EN_DELAY_PLLA Reg Address Bit Field Type Setting Name Description 0x0489 7 0 R W PFD_EN_DE LAY_PLLA Set by CBPro 0x048A 12 8 R W PFD_EN_DE LAY_PLLA Table 16 163 0x048B Reg Address Bit Field Type Setting Name Description 0x048B 19 0 R W HSW_MEAS_SET TLE_PLLA Set by CBPro Table 16 164 0x049B HOLDEXIT_BW_SEL0_PLLA Reg Address Bit Field Type Setting Name Description 0...

Page 222: ...HO_PLLA This group of registers determines the DSPLL A bandwidth used when exiting Holdover Mode Clock Builder Pro will then determine the values for each of these registers Either a full device SOFT_RST_ALL 0x001C 0 or the BW_UPDATE_PLLA bit reg 0x0414 0 must be used to cause all of the BWx_PLLA FAST_BWx_PLLA and BWx_HO_PLLA parameters to take effect Note that the individual SOFT_RST_PLLA 0x001C ...

Page 223: ..._MAX_LIM IT_EN_PLLA Set by CBPro 0x04AC 3 R W HOLD_SET TLE_DET_EN_PLL A Set by CBPro 0x04AD 15 0 R W OUT_MAX_LIM IT_LMT_PLLA Set by CBPro 0x04B1 15 0 R W HOLD_SET TLE_TAR GET_PLLA Set by CBPro Si5397 96 Reference Manual Si5397C D Register Map silabs com Building a more connected world Rev 0 9 223 ...

Page 224: ...Wx_PLLB FAST_BWx_PLLB and BWx_HO_PLLB parameters to take effect Note that individual SOFT_RST_PLLB 0x001C 2 does not update the bandwidth parameters Table 16 172 0x050E 0x0514 DSPLL B Fast Lock Loop Bandwidth Reg Address Bit Field Type Setting Name Description 0x050E 5 0 R W FAST LOCK_BW0_PLLB Parameters that create the fast lock PLL bandwidth 0x050F 5 0 R W FAST LOCK_BW1_PLLB 0x0510 5 0 R W FAST ...

Page 225: ...1D 15 8 R W M_DEN_PLLB 0x051E 23 16 R W M_DEN_PLLB 0x051F 31 24 R W M_DEN_PLLB The loop MA divider denominator values are calculated by ClockBuilder Pro for a particular frequency plan and are written into these registers Table 16 175 0x0520 M Divider Update Bit for PLL B Reg Address Bit Field Type Setting Name Description 0x0520 0 S M_UPDATE_PLLB Must write a 1 to this bit to cause PLL B M divide...

Page 226: ...e integer The FSTEPW value is either added to or subtracted from the feedback M divider Numerator such that an FINC will increase the output frequency and an FDEC will decrease the output frequency See also registers 0x0515 0x051F Table 16 179 0x052A DSPLL B Input Clock Select Reg Address Bit Field Type Setting Name Description 0x052A 0 R W IN_SEL_REGCTRL _PLLB 0 Pin Control 1 Register Control 0x0...

Page 227: ...tion 0x052E 4 0 R W HOLD_HIST_LEN_ PLLB 5 bit value The holdover logic averages the input frequency over a period of time whose duration is determined by the history average length The average frequency is then used as the holdover frequency See to calculate the window length from the register value time 2LEN 1 268nsec Table 16 184 0x052F DSPLLB Holdover History Delay Reg Address Bit Field Type Se...

Page 228: ...le 16 189 0x0537 DSPLLB Input Alarm Masks Reg Address Bit Field Type Setting Name Description 0x0537 3 0 R W IN_LOS_MSK_PLL B For each clock input LOS alarm 0 To use LOS in the clock selection logic 1 To mask LOS from the clock selection logic 0x0537 7 4 R W IN_OOF_MSK_PLL B For each clock input OOF alarm 0 To use OOF in the clock selection logic 1 To mask OOF from the clock selection logic For ea...

Page 229: ...2 3 For priority 3 4 For priority 4 5 7 Reserved Table 16 191 0x0539 DSPLL B Clock Inputs 2 and 3 Priority Reg Address Bit Field Type Setting Name Description 0x0539 2 0 R W IN2_PRIORI TY_PLLB The priority for clock input 2 is 0 No priority 1 For priority 1 2 For priority 2 3 For priority 3 4 For priority 4 5 7 Reserved 0x0539 6 4 R W IN3_PRIORI TY_PLLB The priority for clock input 3 is 0 No prior...

Page 230: ...4 0 R W HSW_COARSE_P M_DLY_PLLB Set by CBPro Table 16 196 0x053F DSPLL B Hold Valid History and Fastlock Status Reg Address Bit Field Type Setting Name Description 0x053F 1 R HOLD_HIST_VAL ID_PLLB Holdover Valid historical frequency data indicator 0 Invalid Holdover History Freerun on input fail or switch 1 Valid Holdover History Holdover on input fail or switch 0x053F 2 R FASTLOCK_STA TUS_PLLB Fa...

Page 231: ...Set by CBPro Table 16 199 0x0588 HSW_FINE_PM_LEN_PLLB Reg Address Bit Field Type Setting Name Description 0x0588 3 0 R W HSW_FINE_PM_LE N_PLLB Table 16 200 0x0589 PFD_EN_DELAY_PLLB Reg Address Bit Field Type Setting Name Description 0x0589 7 0 R W PFD_EN_DE LAY_PLLB Set by CBPro 0x0589 12 8 R W PFD_EN_DE LAY_PLLB Table 16 201 0x058B Reg Address Bit Field Type Setting Name Description 0x058B 19 0 R...

Page 232: ...E 5 0 R W HOLDEX IT_BW1_PLLB Set by CBPro to set the PLL bandwidth when exiting holdover works with HOLDEXIT_BW_SEL0 and HOLD_BW_SEL1 0x059F 5 0 R W HOLDEX IT_BW2_PLLB 0x05A0 5 0 R W HOLDEX IT_BW3_PLLB 0x05A1 5 0 R W HOLDEX IT_BW4_PLLB 0x05A2 5 0 R W HOLDEX IT_BW5_PLLB This group of registers determines the DSPLL B bandwidth used when exiting Holdover Mode In ClockBuilder Pro it is selectable from...

Page 233: ...2 0 R W RAMP_STEP_SIZE _PLLB 0x05A6 3 RAMP_SWITCH_E N_PLLB Table 16 207 0x05AC 0x05B2 Reg Address Bit Field Type Setting Name Description 0x05AC 0 R W OUT_MAX_LIM IT_EN_PLLB Set by CBPro 0x05AC 3 R W HOLD_SET TLE_DET_EN_PLL B Set by CBPro 0x05AD 15 0 R W OUT_MAX_LIM IT_LMT_PLLB Set by CBPro 0x05B1 15 0 R W HOLD_SET TLE_TAR GET_PLLB Set by CBPro Si5397 96 Reference Manual Si5397C D Register Map sil...

Page 234: ...en determine the values for each of these registers Either a full device SOFT_RST_ALL 0x001C 0 or the BW_UPDATE_PLLC bit reg 0x0614 0 must be used to cause all of the BWx_PLLC FAST_BWx_PLLC and BWx_HO_PLLC parameters to take effect Note that individual SOFT_RST_PLLC 0x001C 3 does not update the bandwidth parame ters Table 16 210 0x060E 0x0614 DSPLL C Fast Lock Loop Bandwidth Reg Address Bit Field ...

Page 235: ...0x061C 0x061F MC Divider Denominator for DSPLL C Reg Address Bit Field Type Setting Name Description 0x061C 7 0 R W M_DEN_PLLC 32 bit number 0x061D 15 8 R W M_DEN_PLLC 0x061E 23 16 R W M_DEN_PLLC 0x061F 31 24 R W M_DEN_PLLC The loop MA divider denominator values are calculated by ClockBuilder Pro for a particular frequency plan and are written into these registers Table 16 213 0x0620 M Divider Upd...

Page 236: ...eger The FSTEPW value is either added to or subtracted from the feedback M divider Numerator such that an FINC will increase the output frequency and an FDEC will decrease the output frequency See also Registers 0x0615 0x061F Table 16 217 0x062A DSPLL C Input Clock Select Reg Address Bit Field Type Setting Name Description 0x062A 2 0 R W IN_SEL_PLLC 0 For IN0 1 For IN1 2 For IN2 3 For IN3 4 7 Rese...

Page 237: ...ver logic averages the input frequency over a period of time whose duration is determined by the history average length The average frequency is then used as the holdover frequency See to calculate the window length from the register value time 2LEN 1 268nsec Table 16 222 0x062F DSPLLC Holdover History Delay Reg Address Bit Field Type Setting Name Description 0x062F 4 0 R W HOLD_HIST_DE LAY_PLLC 5...

Page 238: ...Table 16 227 0x0637 DSPLLC Input Alarm Masks Reg Address Bit Field Type Setting Name Description 0x0637 3 0 R W IN_LOS_MSK_PLL C For each clock input LOS alarm 0 To use LOS in the clock selection logic 1 To mask LOS from the clock selection logic 0x0637 7 4 R W IN_OOF_MSK_PLL C For each clock input OOF alarm 0 To use OOF in the clock selection logic 1 To mask OOF from the clock selection logic For...

Page 239: ...2 3 For priority 3 4 For priority 4 5 7 Reserved Table 16 229 0x0639 DSPLL C Clock Inputs 2 and 3 Priority Reg Address Bit Field Type Setting Name Description 0x0639 2 0 R W IN2_PRIORI TY_PLLC The priority for clock input 2 is 0 No priority 1 For priority 1 2 For priority 2 3 For priority 3 4 For priority 4 5 7 Reserved 0x0639 6 4 R W IN3_PRIORI TY_PLLC The priority for clock input 3 is 0 No prior...

Page 240: ...R W HSW_COARSE_P M_DLY_PLLC Set by CBPro Table 16 234 0x063F DSPLL C Hold Valid History and Fastlock Status Reg Address Bit Field Type Setting Name Description 0x063F 1 R HOLD_HIST_VAL ID_PLLC Holdover Valid historical frequency data indicator 0 Invalid Holdover History Freerun on input fail or switch 1 Valid Holdover History Holdover on input fail or switch 0x063F 2 R FASTLOCK_STA TUS_PLLC Fastlo...

Page 241: ...NE_PM_LE N_PLLC Table 16 238 0x0689 PFD_EN_DELAY_PLLC Reg Address Bit Field Type Setting Name Description 0x0689 7 0 R W PFD_EN_DE LAY_PLLC 0x068A 12 8 R W PFD_EN_DE LAY_PLLC Table 16 239 0x068B Reg Address Bit Field Type Setting Name Description 0x068B 19 0 R W HSW_MEAS_SET TLE_PLLC Set by CBPro Table 16 240 0x069B HOLDEXIT_BW_SEL0_PLLC Reg Address Bit Field Type Setting Name Description 0x069B 1...

Page 242: ..._BW2_PLLC 0x06A0 5 0 R W HOLDEX IT_BW3_PLLC 0x06A1 5 0 R W HOLDEX IT_BW4_PLLC 0x06A2 5 0 R W HOLDEX IT_BW5_PLLC This group of registers determines the DSPLL C bandwidth used when exiting Holdover Mode Clock Builder Pro will then determine the values for each of these registers Either a full device SOFT_RST_ALL 0x001C 0 or the BW_UPDATE_PLLC bit reg 0x0614 0 must be used to cause all of the BWx_PLL...

Page 243: ...C 0x06B2 Reg Address Bit Field Type Setting Name Description 0x06AC 0 R W OUT_MAX_LIM IT_EN_PLLC Set by CBPro 0x06AC 3 R W HOLD_SET TLE_DET_EN_PLL C Set by CBPro 0x06AD 15 0 R W OUT_MAX_LIM IT_LMT_PLLC Set by CBPro 0x06B1 15 0 R W HOLD_SET TLE_TAR GET_PLLC Set by CBPro Si5397 96 Reference Manual Si5397C D Register Map silabs com Building a more connected world Rev 0 9 243 ...

Page 244: ... the automatic mode this value will retain its previous value until a valid input clock is presented Note that this value is not meaningful in Holdover or Freerun modes Table 16 247 0x0709 0x070E DSPLL D Loop Bandwidth Reg Address Bit Field Type Setting Name Description 0x0709 5 0 R W BW0_PLLD Parameters that create the normal PLL bandwidth 0x070A 5 0 R W BW1_PLLD 0x070B 5 0 R W BW2_PLLD 0x070C 5 ...

Page 245: ...meters to take effect Note that individual SOFT_RST_PLLD 0x001C 4 does not update the bandwidth parame ters Table 16 249 0x0716 0x071C MD Divider Numerator for DSPLL D Reg Address Bit Field Type Setting Name Description 0x0716 7 0 R W M_NUM_PLLD 56 bit number 0x0717 15 8 R W M_NUM_PLLD 0x0718 23 16 R W M_NUM_PLLD 0x0719 31 24 R W M_NUM_PLLD 0x071A 39 32 R W M_NUM_PLLD 0x071B 47 40 R W M_NUM_PLLD 0...

Page 246: ... Type Setting Name Description 0x0723 0 R W M_FSTEP_MSK_P LLD 0 To enable FINC FDEC updates 1 To disable FINC FDEC updates 0x0723 1 R W M_FSTEPW_DEN_ PLLD 0 Modify numerator 1 Modify denominator Table 16 254 0x0724 0x072A DSPLLD MD Divider Frequency Step Word Reg Address Bit Field Type Setting Name Description 0x0724 7 0 R W M_FSTEPW_PLLD 56 bit number 0x0725 15 8 R W M_FSTEPW_PLLD 0x0726 23 16 R ...

Page 247: ...LOCK_MAN_PLLD 0 For normal operation 1 For force fast lock Table 16 257 0x072D DSPLL D Holdover Control Reg Address Bit Field Type Setting Name Description 0x072D 0 R W HOLD_EN_PLLD 0 Holdover disabled 1 Holdover enabled 0x072D 3 R W HOLD_RAMP_BYP _PLLD Must be set to 1 for normal operation 0x072D 4 R W HOLD_EX IT_BW_SEL1_PLL D 0 To use the fastlock loop BW when exiting from hold over 1 To use the...

Page 248: ...d during entry into holdover The holdover logic pushes back into the past The amount the average window is delayed is the holdover history delay See to calculate the ignore delay time from the register value time 2DELAY 268nsec Table 16 261 0x0732 Reg Address Bit Field Type Setting Name Description 0x0732 4 0 R W HOLD_REF_COUN T_FRC_PLLD 5 bit value Table 16 262 0x0733 0x0735 Reg Address Bit Field...

Page 249: ...e clock selection logic 1 To mask OOF from the clock selection logic For each of the four clock inputs the OOF and or the LOS alarms can be used for the clock selection logic or they can be masked from it Note that the clock selection logic can affect entry into holdover IN0 Input 0 applies to LOS alarm 0x0738 0 OOF alarm 0x0738 4 IN1 Input 1 applies to LOS alarm 0x0738 1 OOF alarm 0x0738 5 IN2 In...

Page 250: ...ty 1 For priority 1 2 For priority 2 3 For priority 3 4 For priority 4 5 7 Reserved 0x073A 6 4 R W IN3_PRIORI TY_PLLD The priority for clock input 3 is 0 No priority 1 For priority 1 2 For priority 2 3 For priority 3 4 For priority 4 5 7 Reserved Table 16 268 0x073B Hitless Switching Mode Reg Address Bit Field Type Setting Name Description 0x073B 1 0 R W HSW_MODE_PLLD 1 Default setting do not modi...

Page 251: ...ck Status Reg Address Bit Field Type Setting Name Description 0x0740 1 R HOLD_HIST_VAL ID_PLLD Holdover Valid historical frequency data indicator 0 Invalid Holdover History Freerun on input fail or switch 1 Valid Holdover History Holdover on input fail or switch 0x0740 2 R FASTLOCK_STA TUS_PLLD Fastlock engaged indicator 0 DSPLL Loop BW is active 1 Fastlock DSPLL BW currently being used Table 16 2...

Page 252: ... 277 0x079B Reg Address Bit Field Type Setting Name Description 0x079B 1 R W IN IT_LP_CLOSE_HO _PLLB 0x079B 2 R W HO_SKIP_PHASE_ PLLD Set by CBPro 0x079B 4 R W HOLD_PRE SERVE_HIST_PLL D Set by CBPro 0x079B 5 R W HOLD_FRZ_WITH_ INTONLY_PLLD Set by CBPro 0x079B 6 R W HOLDEX IT_BW_SEL0_PLL D Set by CBPro 0x079B 7 R W HOLDEX IT_STD_BO_PLLD Set by CBPro Table 16 278 0x079C Reg Address Bit Field Type Se...

Page 253: ...Wx_PLLD and BWx_HO_PLLD parameters to take effect Note that the individu al SOFT_RST_PLLD 0x001C 4 does not update these bandwidth parameters Table 16 280 0x07A4 0x07A5 Reg Address Bit Field Type Setting Name Description 0x07A4 7 0 R W HSW_LIMIT_PLLD Set by CBPro 0x07A5 0 R W HSW_LIMIT_AC TION_PLLD Set by CBPro Table 16 281 0x07A6 Reg Address Bit Field Type Setting Name Description 0x07A6 2 0 R W ...

Page 254: ...e are operating with the optimum signal thresholds Table 16 285 0x0949 Clock Input Control and Configuration Reg Address Bit Field Type Setting Name Description 0x0949 3 0 R W IN_EN 0 Disable and Powerdown Input Buffer 1 Enable Input Buffer for IN3 IN0 0x0949 7 4 R W IN_PULSED_CMO S_EN 0 Standard Input Format 1 Pulsed CMOS Input Format for IN3 IN0 See for more information When a clock is disabled ...

Page 255: ...mmended if changing settings during operation 1 Integer only division best phase noise Recommen ded for Integer N values Note that a device Soft Reset 0x001C 0 1 must be is sued after changing the settings in this register ClockBuilder Pro handles these bits when changing settings for all portions of the device This control bit is only needed when changing the settings for only a portion of the de...

Page 256: ...DIS_ PLLA Clock disable for the fractional divide of the M divider in PLLA Must be set to a 0 if this M divider has a fraction al value 0 Enable the clock to the fractional divide part of the M divider 1 Disable the clock to the fractional divide part of the M divider 0x0B44 5 R W FRACN_CLK_DIS_ PLLB Clock disable for the fractional divide of the M divider in PLLB Must be set to a 0 if this M divi...

Page 257: ... function of the respective inputs ClockBuilder Pro handles these bits when changing settings for all portions of the device This control bit is only needed when changing the settings for only a portion of the device while the remaining portion of the device operates undisturbed Table 16 297 0x0B47 Reg Address Bit Field Type Name Description 0x0B47 4 0 R W OOF_CLK_DIS Table 16 298 0x0B48 Reg Addre...

Page 258: ...e operates undisturbed Table 16 300 0x0B4E Reserved Control Reg Address Bit Field Type Name Description 0x0B4E 7 0 R W RESERVED Internal use for initilization See CBPro Table 16 301 0x0B57 VCO_RESET_CALCODE Reg Address Bit Field Type Name Description 0x0B57 7 0 R W VCO_RESET_CAL CODE 0x0B58 11 8 R W VCO_RESET_CAL CODE Si5397 96 Reference Manual Si5397C D Register Map silabs com Building a more con...

Page 259: ...Bit Field Type Name Description 0x0C06 7 0 R W IN_CLK_VAL_TIME_P LLA Set by CBPro Table 16 306 0x0C07 Reg Address Bit Field Type Name Description 0x0C07 0 R W IN_CLK_VAL_EN _PLLB Set by CBPro Table 16 307 0x0C08 Reg Address Bit Field Type Name Description 0x0C08 7 0 R W IN_CLK_VAL_TIME_P LLB Set by CBPro Table 16 308 0x0C09 Reg Address Bit Field Type Name Description 0x0C09 0 R W IN_CLK_VAL_EN _PL...

Page 260: ... 0x0C0B 0 R W IN_CLK_VAL_EN _PLLD Set by CBPro Table 16 311 0x0C0C Reg Address Bit Field Type Name Description 0x0C0C 7 0 R W IN_CLK_VAL_TIME_P LLD Set by CBPro Si5397 96 Reference Manual Si5397C D Register Map silabs com Building a more connected world Rev 0 9 260 ...

Page 261: ...x0002 7 0 R PN_BASE 0x46 Four digit base part number one nibble per digit Example Si5396A A GM The base part num ber OPN is 5396 which is stored in this regis ter 0x0003 15 8 R PN_BASE 0x53 Table 17 4 0x0004 Device Grade Reg Address Bit Field Type Setting Name Description 0x0004 7 0 R GRADE One ASCII character indicating the device speed synthesis mode 0 A 1 B 2 C 3 D 10 J 11 K 12 L 13 M Refer to ...

Page 262: ...ncy plan and all other operating characteristics defined by the user s ClockBuilder Pro project file Si5396C A GM Applies to a base or non custom OPN device Base devices are factory pre programmed to a specific base part type e g Si5396 but exclude any user defined frequency plan or other user defined operating characteristics selected in ClockBuilder Pro Table 17 8 0x000B I2C Address Reg Address ...

Page 263: ...tion 0x000E 1 0 R LOL_PLL B A 1 if the DSPLL is out of lock 0x000E 5 4 R HOLD_PLL B A 1 if the DSPLL is in holdover or free run DSPLL_A corresponds to bit 0 4 DSPLL_B corresponds to bit 1 5 Table 17 12 0x000F INCAL Status Reg Address Bit Field Type Setting Name Description 0x000F 5 4 R CAL_PLL B A 1 if the DSPLL internal calibration is busy DSPLL_A corresponds to bit 4 DSPLL_B corresponds to bit 5...

Page 264: ...d 0x0013 5 4 R W HOLD_FLG_PLL B A 1 if the DSPLL was in holdover or freerun Sticky flag versions of address 0x000E DSPLL_A corresponds to bit 0 4 DSPLL_B corresponds to bit 1 5 Table 17 16 0x0014 INCAL Flags Reg Address Bit Field Type Setting Name Description 0x0014 5 4 R W CAL_FLG_PLL B A 1 if the DSPLL internal calibration was busy These are sticky flag versions of 0x000F DSPLL A corresponds to ...

Page 265: ...R_MSK 0x0018 2 OOF_IN_INTR_MSK 0x0018 6 Input 3 IN3 corresponds to LOS_IN_INTR_MSK 0x0018 3 OOF_IN_INTR_MSK 0x0018 7 These are the interrupt mask bits for the OOF and LOS flags in register 0x0012 If a mask bit is set the alarm will be blocked from causing an interrupt Table 17 20 0x0019 Holdover and LOL Masks Reg Address Bit Field Type Setting Name Description 0x0019 1 0 R W LOL_INTR_MSK_P LL B A ...

Page 266: ...ecrement Table 17 24 0x001E Sync Power Down and Hard Reset Reg Address Bit Field Type Setting Name Description 0x001E 0 R W PDN 1 to put the device into low power mode 0x001E 1 S HARD_RST Perform Hard Reset with NVM read 0 Normal Operation 1 Hard Reset the device 0x001E 2 S SYNC 1 to reset all the R dividers to the same state Table 17 25 0x0020 DSPLL_SEL 1 0 Control of FINC FDEC for DCO Reg Addres...

Page 267: ...s of Signal Re Qualification Value Reg Address Bit Field Type Setting Name Description 0x002D 1 0 R W LOS0_VAL_TIME Clock Input 0 0 For 2 msec 1 For 100 msec 2 For 200 msec 3 For one second 0x002D 3 2 R W LOS1_VAL_TIME Clock Input 1 same as above 0x002D 5 4 R W LOS2_VAL_TIME Clock Input 2 same as above 0x002D 7 6 R W LOS3_VAL_TIME Clock Input 3 same as above When an input clock is gone and therefo...

Page 268: ...ger value for Input 3 given a particular frequency plan Table 17 33 0x0036 0x0037 LOS0 Clear Threshold Reg Address Bit Field Type Setting Name Description 0x0036 7 0 R W LOS0_CLR_THR 16 bit Threshold Value 0x0037 15 8 R W LOS0_CLR_THR ClockBuilder Pro calculates the correct LOS register clear threshold value for Input 0 given a particular frequency plan Table 17 34 0x0038 0x0039 LOS1 Clear Thresho...

Page 269: ... CBPro Table 17 38 0x003F OOF Enable Reg Address Bit Field Type Setting Name Description 0x003F 3 0 R W OOF_EN 0 To disable 1 To enable 0x003F 7 4 R W FAST_OOF_EN bit 0 4 correspond to IN0 bit 1 5 correspond to IN1 bit 2 6 correspond to IN2 bit 3 7 correspond to IN3 Table 17 39 0x0040 OOF Reference Select Reg Address Bit Field Type Setting Name Description 0x0040 2 0 R W OOF_REF_SEL 0 IN0 1 IN1 2 ...

Page 270: ... 1 16 ppm 0x0049 7 0 R W OOF3_SET_THR OOF Set threshold Range is up to 500 ppm in steps of 1 16 ppm Table 17 42 0x004A 0x004D Out of Frequency Clear Threshold Reg Address Bit Field Type Setting Name Description 0x004A 7 0 R W OOF0_CLR_THR OOF Clear threshold Range is up to 500 ppm in steps of 1 16 ppm 0x004B 7 0 R W OOF1_CLR_THR OOF Clear threshold Range is up to 500 ppm in steps of 1 16 ppm 0x004...

Page 271: ... 46 0x0055 0x0058 Reg Address Bit Field Type Setting Name Description 0x0055 3 0 R W FAST_OOF0_CLR_ THR 1 Value x 1000 ppm 0x0056 3 0 R W FAST_OOF1_CLR_ THR 0x0057 3 0 R W FAST_OOF2_CLR_ THR 0x0058 3 0 R W FAST_OOF3_CLR_ THR Table 17 47 0x0059 Fast OOF Detection Windows Reg Address Bit Field Type Setting Name Description 0x0059 1 0 R W FAST_OOF0_DET WIN_SEL Values calculated by CBPro 0x0059 3 2 R ...

Page 272: ...Name Description 0x0062 7 0 R W OOF2_RATIO_REF Values calculated by ClockBuilder Pro 0x0063 15 8 R W OOF2_RATIO_REF 0x0064 23 16 R W OOF2_RATIO_REF 0x0065 25 24 R W OOF2_RATIO_REF Table 17 51 0x0066 0x0069 OOF3 Ratio for Reference Reg Address Bit Field Type Setting Name Description 0x0066 7 0 R W OOF3_RATIO_REF Values calculated by ClockBuilder Pro 0x0067 15 8 R W OOF3_RATIO_REF 0x0068 23 16 R W O...

Page 273: ... Field Type Setting Name Description 0x0096 3 0 R W LOL_FST_SET_TH R_SEL_PLLA Values calculated by CBPro 0x0096 7 4 R W LOL_FST_SET_TH R_SEL_PLLB Table 17 56 0x0098 Fast LOL Clear Threshold Reg Address Bit Field Type Setting Name Description 0x0098 3 0 R W LOL_FST_CLR_TH R_SEL_PLLA Values calculated by CBPro 0x0098 7 4 R W LOL_FST_CLR_TH R_SEL_PLLB Table 17 57 0x009A LOL Enable Reg Address Bit Fie...

Page 274: ...holds See list be low for selectable values 0x009E 7 4 R W LOL_SLW_SET_TH R_PLLB Configures the loss of lock set thresholds See list be low for selectable values Table 17 61 0x00A0 LOL Clear Thresholds Reg Address Bit Field Type Setting Name Description 0x00A0 3 0 R W LOL_SLW_CLR_TH R_PLLA Configures the loss of lock clear thresholds See list be low for selectable values 0x00A0 7 4 R W LOL_SLW_CLR...

Page 275: ...56_PLLB 0x00AB 23 16 R W LOL_CLR_DE LAY_DIV256_PLLB 0x00AC 28 24 R W LOL_CLR_DE LAY_DIV256_PLLB ClockBuilder Pro is used to set these values Table 17 65 0x00E2 Active NVM Bank Reg Address Bit Field Type Setting Name Description 0x00E2 7 0 R AC TIVE_NVM_BLANK 0x03 when no NVM has been burned 0x0F when 1 NVM bank has been burned 0x3F when 2 NVM banks have been burned When ACTIVE_NVM_BANK 0x3F the la...

Page 276: ...nimize the phase tran sients when switching the PLL bandwidth See FAST LOCK_EXTEND_SCL_PLLx 0x00EB 15 8 R W FSTLK_TIM ER_EXT_PLLB 0x00EC 23 16 R W FSTLK_TIM ER_EXT_PLLB 0x00ED 28 24 R W FSTLK_TIM ER_EXT_PLLB Table 17 69 0x00F6 Reg Address Bit Field Type Name Description 0x00F6 0 R REG_0XF7_INT R Set by CBPro 0x00F6 1 R REG_0XF8_INT R Set by CBPro 0x00F6 2 R REG_0XF9_INT R Set by CBPro Table 17 70 ...

Page 277: ...g Name Description 0x00FE 7 0 R DEVICE_READY Ready Only byte to indicate device is ready When read data is 0x0F one can safely read write registers This register is repeated on every page so that a page write is not ever required to read the DEVICE_READY sta tus WARNING Any attempt to read or write any register other than DEVICE_READY before DEVICE_READY reads as 0x0F may corrupt the NVM programmi...

Page 278: ...0112 0x0117 0x0126 0x012B 1 R W OUT0_OE OUT1_OE OUT2_OE OUT3_OE 0 To disable the output 1 To enable the output 0x0112 0x0117 0x0126 0x012B 2 R W OUT0_RDIV_ FORCE OUT1_RDIV_ FORCE OUT2_RDIV_ FORCE OUT3_RDIV_ FORCE Force Rx output divider divide by 2 0 Rx_REG sets divide value default 1 Divide value forced to divide by 2 The output drivers are all identical Table 17 76 0x0113 0x0118 0x0127 0x012C Ou...

Page 279: ...n 0x0114 0x0119 0x0128 0x012D 3 0 R W OUT0_CM OUT1_CM OUT2_CM OUT3_CM OUTx common mode voltage selection This field only applies when OUTx_FORMAT 1 or 2 See 0x0114 0x0119 0x0128 0x012D 6 4 R W OUT0_AMPL OUT1_AMPL OUT2_AMPL OUT3_AMPL OUTx common mode voltage selection This field only applies when OUTx_FORMAT 1 or 2 See ClockBuilder Pro is used to select the correct settings for this register The ou...

Page 280: ...L are different when selecting the same DSPLL OUTx_DIS_SRC OUTx_MUX_SEL 1 Table 17 79 0x0116 0x011B 0x012A 0x012F Output Disable Source DSPLL Reg Address Bit Field Type Setting Name Description 0x0116 0x011B 0x012A 0x012F 2 0 R W OUT0_DIS_SRC OUT1_DIS_SRC OUT2_DIS_SRC OUT3_DIS_SRC Output clock Squelched temporary disable on DSPLL Soft Reset 0 Reserved 1 DSPLL A squelches output 2 DSPLL B squelches...

Page 281: ...bled on LOSXAXB 1 All outputs remain enabled during LOSXAXB condi tion 0x0141 7 R W OUT_DIS_MSK_LO S_PFD Table 17 82 0x0142 Output Disable Loss of Lock PLL Reg Address Bit Field Type Setting Name Description 0x0142 1 0 R W OUT_DIS_MSK_LO L_PLL B A 0 LOL will disable all connected outputs 1 LOL does not disable any outputs 0x0142 5 4 R W OUT_DIS_MSK_H OLD_PLL B A Bit 0 LOL_DSPLL_A mask Bit 1 LOL_DS...

Page 282: ...een in ClockBuilder Pro calcu lates the correct values for the P dividers Table 17 85 0x020E 0x0211 P0 Divider Denominator Reg Address Bit Field Type Setting Name Description 0x020E 7 0 R W P0_DEN 32 bit Integer Number 0x020F 15 8 R W P0_DEN 0x0210 23 16 R W P0_DEN 0x0211 31 24 R W P0_DEN The P1 P2 and P3 divider numerator and denominator follow the same format as P0 described above ClockBuilder P...

Page 283: ...d SOFT_RST_PLLB do not update the Px_NUM or Px_DEN values Table 17 88 0x0231 P0 Factional Division Enable Reg Address Bit Field Type Setting Name Description 0x0231 3 0 R W P0_FRACN_MODE P0 IN0 input divider fractional mode Must be set to 0xB for proper operation 0x0231 4 R W P0_FRAC_EN P0 IN0 input divider fractional enable 0 Integer only division 1 Fractional or Integer division Table 17 89 0x02...

Page 284: ...UM Note that changing this register during operation may cause indefinite loss of lock unless the guidelines in are followed Table 17 93 0x023B 0x023E MXAXB Divider Denominator Reg Address Bit Field Type Setting Name Description 0x023B 7 0 R W MXAXB_DEN 32 bit Integer Number 0x023C 15 8 R W MXAXB_DEN 0x023D 23 16 R W MXAXB_DEN 0x023E 31 24 R W MXAXB_DEN The M divider numerator and denominator are ...

Page 285: ...er 0x0250 0x0252 0x025F 0x0261 R3_REG 24 bit Integer Number 0x0250 0x0252 Table 17 97 0x026B 0x0272 Design Identifier Reg Address Bit Field Type Setting Name Description 0x026B 7 0 R W DESIGN_ID0 ASCII encoded string defined by ClockBuilder Pro user with user defined space or null padding of unused char acters A user will normally include a configuration ID revision ID For example ULT 1A with null...

Page 286: ...ic base part type e g Si5396 but exclude any user defined frequency plan or other user defined operating characteristics selected in ClockBuilder Pro Table 17 99 0x027D Reg Address Bit Field Type Setting Name Description 0x027D 7 0 R W OPN_REVISION Table 17 100 0x027E Reg Address Bit Field Type Setting Name Description 0x027E 7 0 R W BASELINE_ID Table 17 101 0x028A 0x028D Reg Address Bit Field Typ...

Page 287: ... precision from 2 ppm to 0 0625 ppm 0x0291 4 0 R W OOF3_CLR_THR_ EXT The OOF3 clear threshold extension increases thresh old precision from 2 ppm to 0 0625 ppm Table 17 104 0x0294 Reg Address Bit Field Type Setting Name Description 0x0294 3 0 R W FASTLOCK_EX TEND_SCL_PLLA Scales LOLB_INT_TIMER_DIV256 Set by CBPro 0x0294 7 4 R W FASTLOCK_EX TEND_SCL_PLLB Table 17 105 0x0296 Reg Address Bit Field Ty...

Page 288: ...W FAST LOCK_DLY_ON LOL_PLLA Table 17 109 0x029D 0x29F Reg Address Bit Field Type Setting Name Description 0x029D 7 0 R W FAST LOCK_DLY_ON LOL_PLLB Set by CBPro 0x029E 15 8 R W FAST LOCK_DLY_ON LOL_PLLB 0x029F 19 16 R W FAST LOCK_DLY_ON LOL_PLLB Table 17 110 0x02A6 0x2A8 Reg Address Bit Field Type Setting Name Description 0x02A6 7 0 R W FAST LOCK_DLY_ONSW _PLLA Set by CBPro 0x02A7 15 8 R W FAST LOC...

Page 289: ...PLLB Table 17 113 0x02B8 Reg Address Bit Field Type Setting Name Description 0x02B8 0 R W LOL_LOS_REFCLK _PLLA Set by CBPro 0x02B8 1 R W LOL_LOS_REFCLK _PLLB Set by CBPro Table 17 114 0x02B9 Reg Address Bit Field Type Setting Name Description 0x02B9 0 R W LOL_LOS_REFCLK _PLLA_FLG Set by CBPro 0x02B9 1 R W LOL_LOS_REFCLK _PLLB_FLG Set by CBPro Table 17 115 0x02BC Reg Address Bit Field Type Setting ...

Page 290: ...Name Description 0x030C 0 S N0_UPDATE Set this bit to latch the N output divider registers into operation Setting this self clearing bit to 1 latches the new N output divider register values into operation A Soft Reset will have the same effect Table 17 119 that Follow the N0_NUM and N0_DEN Definitions Reg Address Description Size Same as Address 0x030D 0x0312 N1_NUM 44 bit Integer 0x0302 0x0307 0...

Page 291: ...ritten all other bits in this register must be written as zeros ClockBuilder Pro handles these updates when changing settings for all portions of the device This control bit is only needed when changing the settings for only a portion of the device while the remaining portion of the device operates undisturbed Si5397 96 Reference Manual Si5396 Register Map silabs com Building a more connected worl...

Page 292: ... SOFT_RST_ALL 0x001C 0 or the BW_UPDATE_PLLA bit reg 0x0414 0 must be used to cause all of the BWx_PLLA FAST_BWx_PLLA and BWx_HO_PLLA parameters to take effect Note that individual SOFT_RST_PLLA 0x001C 1 does not update the bandwidth parame ters Appendix A Custom Differential Amplitude Controls The loop bandwidth values are calculated by ClockBuilder Pro and written into these registers Table 17 1...

Page 293: ..._DEN_PLLA 32 bit number 0x041D 15 8 R W M_DEN_PLLA 0x041E 23 16 R W M_DEN_PLLA 0x041F 31 24 R W M_DEN_PLLA The loop MA divider denominator values are calculated by ClockBuilder Pro for a particular frequency plan and are written into these registers Table 17 126 0x0420 M Divider Update Bit for PLL A Reg Address Bit Field Type Setting Name Description 0x0420 0 S M_UPDATE_PLLA Must write a 1 to this...

Page 294: ...ed to or subtracted from the feedback M divider Numerator such that an FINC will increase the output frequency and an FDEC will decrease the output frequency See also Registers 0x0415 0x041F Table 17 130 0x042A DSPLL A Input Clock Select Reg Address Bit Field Type Setting Name Description 0x042A 2 0 R W IN_SEL_PLLA 0 For IN0 1 For IN1 2 For IN2 3 For IN3 4 7 Reserved This is the input clock select...

Page 295: ...during entry into holdover The holdover logic pushes back into the past The amount the average window is delayed is the holdover history delay See to calculate the ignore delay time from the register value time 2DELAY 268nsec Table 17 134 0x0431 Reg Address Bit Field Type Setting Name Description 0x0431 4 0 R W HOLD_REF_COUN T_FRC_PLLA 5 bit value Table 17 135 0x0432 Reg Address Bit Field Type Set...

Page 296: ...the clock selection logic 1 To mask OOF from the clock selection logic For each of the four clock inputs the OOF and or the LOS alarms can be used for the clock selection logic or they can be masked from it Note that the clock selection logic can affect entry into holdover IN0 Input 0 applies to LOS alarm 0x0437 0 OOF alarm 0x0437 4 IN1 Input 1 applies to LOS alarm 0x0437 1 OOF alarm 0x0437 5 IN2 ...

Page 297: ...ity 1 For priority 1 2 For priority 2 3 For priority 3 4 For priority 4 5 7 Reserved 0x0439 6 4 R W IN3_PRIORI TY_PLLA The priority for clock input 3 is 0 No priority 1 For priority 1 2 For priority 2 3 For priority 3 4 For priority 4 5 7 Reserved Table 17 141 0x043A Hitless Switching Mode Reg Address Bit Field Type Setting Name Description 0x043A 1 0 R W HSW_MODE_PLLA 1 Default setting do not mod...

Page 298: ...ta indicator 0 Invalid Holdover History Freerun on input fail or switch 1 Valid Holdover History Holdover on input fail or switch 0x043F 2 R O FASTLOCK_STA TUS_PLLA Fastlock engaged indicator 0 DSPLL Loop BW is active 1 Fastlock DSPLL BW currently being used When the input fails or is switched and the DSPLL switches to Holdover or Freerun mode HOLD_HIST_VALID_PLLA accumulation will stop When a val...

Page 299: ...e 17 150 0x048B Reg Address Bit Field Type Setting Name Description 0x048B 19 0 R W HSW_MEAS_SET TLE_PLLA Set by CBPro Table 17 151 0x049B HOLDEXIT_BW_SEL0_PLLA Reg Address Bit Field Type Setting Name Description 0x049B 1 R W IN IT_LP_CLOSE_HO _PLLA Set by CBPro 0x049B 2 R W HO_SKIP_PHASE_ PLLA Set by CBPro 0x049B 4 R W HOLD_PRE SERVE_HIST_PLL A Set by CBPro 0x049B 5 R W HOLD_FRZ_WITH_ INTONLY_PLL...

Page 300: ... 17 154 0x04A4 0x04A5 Reg Address Bit Field Type Setting Name Description 0x04A4 7 0 R W HSW_LIMIT_PLLA Set by CBPro 0x04A5 0 R W HSW_LIMIT_AC TION_PLLA Set by CBPro Table 17 155 0x04A6 Reg Address Bit Field Type Setting Name Description 0x04A6 2 0 R W RAMP_STEP_SIZE _PLLA 0x04A6 3 R W RAMP_SWITCH_E N_PLLA Table 17 156 0x04AC 0x04B2 Reg Address Bit Field Type Setting Name Description 0x04AC 0 R W ...

Page 301: ... 0 must be used to cause all of the BWx_PLLB FAST_BWx_PLLB and BWx_HO_PLLB parameters to take effect Note that individual SOFT_RST_PLLB 0x001C 2 does not update the bandwidth parame ters Table 17 159 0x050E 0x0514 DSPLL B Fast Lock Loop Bandwidth Reg Address Bit Field Type Setting Name Description 0x050E 5 0 R W FAST LOCK_BW0_PLLB Parameters that create the fast lock PLL bandwidth 0x050F 5 0 R W F...

Page 302: ...bit number 0x051D 15 8 R W M_DEN_PLLB 0x051E 23 16 R W M_DEN_PLLB 0x051F 31 24 R W M_DEN_PLLB The loop MA divider denominator values are calculated by ClockBuilder Pro for a particular frequency plan and are written into these registers Table 17 162 0x0520 M Divider Update Bit for PLL B Reg Address Bit Field Type Setting Name Description 0x0520 0 S M_UPDATE_PLLB Must write a 1 to this bit to cause...

Page 303: ...from the feedback M divider Numerator such that an FINC will increase the output frequency and an FDEC will decrease the output frequency See also Registers 0x0515 0x051F Table 17 166 0x052A DSPLL B Input Clock Select Reg Address Bit Field Type Setting Name Description 0x052A 3 1 R W IN_SEL_PLLB 0 For IN0 1 For IN1 2 For IN2 3 For IN3 4 7 Reserved 0x052A 0 R W IN_SEL_REGCTRL _PLLB 0 Pin Control 1 ...

Page 304: ...dow length from the register value time 2LEN 1 268nsec Table 17 170 0x052F DSPLLB Holdover History Delay and Fastlock Status Reg Address Bit Field Type Setting Name Description 0x052F 4 0 R HOLD_HIST_DE LAY_PLLB 5 bit value The most recent input frequency perturbations can be ignored during entry into holdover The holdover logic pushes back into the past The amount the average window is delayed is...

Page 305: ...0 R W IN_LOS_MSK_PLL B For each clock input LOS alarm 0 To use LOS in the clock selection logic 1 To mask LOS from the clock selection logic 0x0537 7 4 R W IN_OOF_MSK_PLL B For each clock input OOF alarm 0 To use OOF in the clock selection logic 1 To mask OOF from the clock selection logic For each of the four clock inputs the OOF and or the LOS alarms can be used for the clock selection logic or ...

Page 306: ... 2 3 For priority 3 4 For priority 4 5 7 Reserved Table 17 177 0x0539 DSPLL B Clock Inputs 2 and 3 Priority Reg Address Bit Field Type Setting Name Description 0x0539 2 0 R W IN2_PRIORI TY_PLLB The priority for clock input 2 is 0 No priority 1 For priority 1 2 For priority 2 3 For priority 3 4 For priority 4 5 7 Reserved 0x0539 6 4 R W IN3_PRIORI TY_PLLB The priority for clock input 3 is 0 No prio...

Page 307: ...ion 0x053E 4 0 R W HSW_COARSE_P M_DLY_PLLB Set by CBPro Table 17 182 0x053F DSPLL B Hold Valid History Reg Address Bit Field Type Setting Name Description 0x053F 1 R W HOLD_HIST_VAL ID_PLLB Holdover Valid historical frequency data indicator 0 Invalid Holdover History Freerun on input fail or switch 1 Valid Holdover History Holdover on input fail or switch 0x053F 2 R FASTLOCK_STA TUS_PLLB Fastlock ...

Page 308: ... 1 R W FORCE_FINE_ADJ _PLLB Set by CBPro Table 17 185 0x0588 Reg Address Bit Field Type Setting Name Description 0x0588 3 0 R W HSW_FINE_PM_LE N_PLLB Table 17 186 0x0589 Reg Address Bit Field Type Setting Name Description 0x0589 7 0 R W PFD_EN_DE LAY_PLLB 0x0589 12 8 R W PFD_EN_DE LAY_PLLB Table 17 187 0x058B Reg Address Bit Field Type Setting Name Description 0x058B 19 0 R W HSW_MEAS_SET TLE_PLLB...

Page 309: ...s Bit Field Type Setting Name Description 0x059C 6 R W HOLDEX IT_ST_BO_PLLB Set by CBPro 0x059C 7 R W HOLD_RAMPBP_N OHIST_PLLB Set by CBPro Table 17 190 0x059D Reg Address Bit Field Type Setting Name Description 0x059D 5 0 R W HOLDEX IT_BW0_PLLB Table 17 191 0x059E Reg Address Bit Field Type Setting Name Description 0x059E 5 0 R W HOLDEX IT_BW1_PLLB Table 17 192 0x059F Reg Address Bit Field Type S...

Page 310: ... W HSW_LIMIT_PLLB Set by CBPro 0x05A5 0 R W HSW_LIMIT_AC TION_PLLB Set by CBPro Table 17 197 0x05A6 Reg Address Bit Field Type Setting Name Description 0x05A6 2 0 R W RAMP_STEP_SIZE _PLLB 0x05A6 3 R W RAMP_SWITCH_E N_PLLB Table 17 198 0x05AC 0x05B2 Reg Address Bit Field Type Setting Name Description 0x05AC 0 R W OUT_MAX_LIM IT_EN_PLLB Set by CBPro 0x05AC 3 R W HOLD_SET TLE_DET_EN_PLL B Set by CBPr...

Page 311: ...e are operating with the optimum signal thresholds Table 17 201 0x0949 Clock Input Control and Configuration Reg Address Bit Field Type Setting Name Description 0x0949 3 0 R W IN_EN 0 Disable and Powerdown Input Buffer 1 Enable Input Buffer for IN3 IN0 0x0949 7 4 R W IN_PULSED_CMO S_EN 0 Standard Input Format 1 Pulsed CMOS Input Format for IN3 IN0 See for more information When a clock is disabled ...

Page 312: ...ging settings during operation 1 Integer only division best phase noise Recommen ded for Integer N values Note that a device Soft Reset 0x001C 0 1 must be is sued after changing the settings in this register ClockBuilder Pro handles these bits when changing settings for all portions of the device This control bit is only needed when changing the settings for only a portion of the device while the ...

Page 313: ...ock to the fractional divide part of the P divider 0x0B44 4 R W FRACN_CLK_DIS_ PLLA Clock disable for the fractional divide of the M divider in PLLA Must be set to a 0 if this M divider has a fraction al value 0 Enable the clock to the fractional divide part of the M divider 1 Disable the clock to the fractional divide part of the M divider 0x0B44 5 R W FRACN_CLK_DIS_ PLLB Clock disable for the fr...

Page 314: ..._CLK_DI S Set by CBPro Table 17 215 0x0B4A Divider Clock Disables Reg Address Bit Field Type Name Description 0x0B4A 4 0 R W N_CLK_DIS Disable internal dividers for PLLs B A Must be set to 0 to use the DSPLL See related registers 0x0A03 and 0x0A05 ClockBuilder Pro handles these bits when changing settings for all portions of the device This control bit is only needed when changing the settings for...

Page 315: ...ss Bit Field Type Name Description 0x0C05 0 R W IN_CLK_VAL_EN_PLLA Set by CBPro Table 17 221 0x0C06 Reg Address Bit Field Type Name Description 0x0C06 7 0 R W IN_CLK_VAL_TIME_P LLA Set by CBPro Table 17 222 0x0C07 Reg Address Bit Field Type Name Description 0x0C07 0 R W IN_CLK_VAL_EN _PLLB Set by CBPro Table 17 223 0x0C08 Reg Address Bit Field Type Name Description 0x0C08 7 0 R W IN_CLK_VAL_TIME_P...

Page 316: ...9 June 2019 Updated CMOS input buffer section Added information for internal reference devices Revision 0 1 June 2018 Intitial Release Si5397 96 Reference Manual Revision History silabs com Building a more connected world Rev 0 9 316 ...

Page 317: ...Class III devices applications for which FDA premarket approval is required or Life Support Systems without the specific written consent of Silicon Labs A Life Support System is any product or system intended to support or sustain life and or health which if it fails can be reasonably expected to result in significant personal injury or death Silicon Labs products are not designed or authorized fo...

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