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Technology functions
3.1 High-speed counters
CPU 1512C-1 PN (6ES7512-1CK01-0AB0)
50
Manual, 12/2017, A5E40898741-AA
3.1.2.3
Assignment of the feedback interface of the high-speed counters
The user program receives current values and status information from the high speed
counter via the feedback interface.
Note
Operation with High_Speed_Counter technology object
The High_Speed_Counter technology object is available for high-speed counting mode. We
therefore recommend use of the technology object High_Speed_Counter instead of the
control interface/feedback interface for controlling the high speed counter.
For information on configuring the technology object and programming the associated
instruction, refer to the S7-1500, ET 200MP, ET 200SP Counting, measurement and position
detection (
http://support.automation.siemens.com/WW/view/en/59709820
) function manual.
Feedback interface per channel
The following table shows the feedback interface assignment:
Table 3- 4
Assignment of the feedback interface
Offset from start
address
Parameter
Meaning
Bytes 0 to 3
COUNT VALUE
Current count value
Bytes 4 to 7
CAPTURED VALUE
Last Capture value acquired
Bytes 8 to 11
MEASURED VALUE
Current measured value
Byte 12
–
Bits 3 to 7: Reserve; set to 0
LD_ERROR
Bit 2: Error when loading via control interface
ENC_ERROR
Bit 1: Incorrect encoder signal
POWER_ERROR
Bit 0: Incorrect supply voltage L+
Byte 13
–
Bits 6 to 7: Reserve; set to 0
STS_SW_GATE
Bit 5: Software gate status
STS_READY
Bit 4: Digital on-board I/O started up and parameters assigned
LD_STS_SLOT_1
Bit 3: Load request for Slot 1 detected and executed (toggling)
LD_STS_SLOT_0
Bit 2: Load request for Slot 0 detected and executed (toggling)
RES_EVENT_ACK
Bit 1: Reset of event bits active
–
Bit 0: Reserve; set to 0
Byte 14
STS_DI2
Bit 7: Reserve; set to 0
STS_DI1
Bit 6: Status HSC DI1
STS_DI0
Bit 5: Status HSC DI0
STS_DQ1
Bit 4: Status HSC DQ1
STS_DQ0
Bit 3: Status HSC DQ0
STS_GATE
Bit 2: Internal gate status
STS_CNT
Bit 1: Count pulse detected within last approx. 0.5 s
STS_DIR
Bit 0: Direction of last count value change
Summary of Contents for Simatic S7-1500 CPU 1512C-1 PN
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