Technology functions
3.1 High-speed counters
CPU 1512C-1 PN (6ES7512-1CK01-0AB0)
48
Manual, 12/2017, A5E40898741-AA
Control interface per channel
The following table shows the control interface assignment:
Table 3- 3
Assignment of the control interface
Offset from start
address
Parameter
Meaning
Bytes 0 to 3
Slot 0
Load value (meaning of the value is specified in LD_SLOT_0)
Bytes 4 to 7
Slot 1
Load value (meaning of the value is specified in LD_SLOT_1)
Byte 8
LD_SLOT_0*
Specifies the meaning of the value in Slot 0
Bit 3
Bit 2 Bit 1 Bit 0
0
0
0
0
No action, idle state
0
0
0
1
Load counter
0
0
1
0
Reserve
0
0
1
1
Load start value
0
1
0
0
Load comparison value 0
0
1
0
1
Load comparison value 1
0
1
1
0
Load low counting limit
0
1
1
1
Load high counting limit
1
0
0
0
Reserve
to
1
1
1
1
LD_SLOT_1*
Specifies the meaning of the value in Slot 1
Bit 7
Bit 6 Bit 5 Bit 4
0
0
0
0
No action, idle state
0
0
0
1
Load counter
0
0
1
0
Reserve
0
0
1
1
Load start value
0
1
0
0
Load comparison value 0
0
1
0
1
Load comparison value 1
0
1
1
0
Load low counting limit
0
1
1
1
Load high counting limit
1
0
0
0
Reserve
to
1
1
1
1
Byte 9
EN_CAPTURE
Bit 7: Enable capture function
EN_SYNC_DN
Bit 6: Enable downward synchronization
EN_SYNC_UP
Bit 5: Enable upward synchronization
SET_DQ1
Bit 4: Set DQ1
SET_DQ0
Bit 3: Set DQ0
TM_CTRL_DQ1
Bit 2: Enable technological function DQ1
TM_CTRL_DQ0
Bit 1: Enable technological function DQ0
SW_GATE
Bit 0: Software gate
Summary of Contents for Simatic S7-1500 CPU 1512C-1 PN
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