XRIO
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Operating Manual XCx 300 / 500 / 540 Version 09/08
6.2
Addressing I/O Modules
In input addressing the debounced and non-debounced inputs are
always directly after one another.
Input debouncing at 2 ms input signal delay is realized by
software in the RIO bus coupler. (The inputs on the I/O modules
are additionally debounced with 01,ms).
In output addressing, even modules with just 1 byte outputs
always occupy 1 word.
This ensures an even start address for the following modules.
Module
RIO 16I
RIO 8I/8I/O
RIO 8I/O
RIO 16O
Inputs not debounced
IB0, IB1
IB4, IB5
IB8
-
Inputs debounced
IB2, IB3
IB6, IB7
IB9
-
Outputs
-
QB1(+QB0) QB3(+QB2)
QB4, QB5
6.3
XRIO Flags in Shared Memory Validity of Process Data
Use the shared memory flags
plcMem.plcSect.flgXRIO.bXRio[]
ARRAY[1..4] OF BOOL
or
cmpSflgXRIO_bXRio[]
ARRAY[1..4] OF BOOL
to check the validity of XRIO process data
TRUE = Input image valid (PLC mode RUN, no communication error)
FALSE = Input image invalide (PLC mode STOP, not ready or
communication error)
