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Specification of SN200G high-performance vector convertor Appendix
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FD-05 is set as 1 :
ADR 01H
CMD 03H
Byte No. 04H
Data F002H high-order 00H
Data F002H low-order 00H
Data F003H high-order 00H
Data F003H low-order 01H
CRC CHK low-order
CRC CHK value to be calculated
CRC CHK high-order
CMD code: 06H, write one word. For example: write 5000 (1388H) in F00AH address of
frequency convertor with slave address being 02H.
CMD message of host
ADR 02H
CMD 06H
Data address high-order F0H
Data address low-order
0AH
Data content high-order 13H
Data content low-order 88H
CRC CHK low-order
CRC CHK value to be calculated
CRC CHK high-order
Response message of slave
ADR 02H
CMD 06H
Data address high-order F0H
Data address low-order 0AH
Data content high-order 13H
Data content low-order
88H
CRC CHK low-order
CRC CHK value to be calculated
CRC CHK high-order
Verification mode-CRC verification mode: CRC (Cyclical Redundancy Check) uses RTU frame
format, and message includes error detection domain based on CRC method. CRC domain detects the
contents of whole message. CRC domain is two-byte and includes 16-bit binary system value. It’s added
to message after calculation by transmission equipment. Receiving equipment recalculates CRC of
received message and compares with value in received CRC domain. If two CRC values are not equal,
the transmission is wrong.
CRC firstly stores 0xFFFF, and then calls a course to process successive 8-bit bytes in message
and value in current register. Only 8Bit data in each character is valid for CRC, start bit, stop bit and
parity check bit are invalid.