RTD Embedded Technologies, Inc.
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32
DM35425HR User’s Manual
6.1.7
GBC_SYS_CLK_FREQ
(R
EAD
O
NLY
)
This register contains the measured frequency of the system clock. Units are 10 kHz, i.e. (Frequency in Hertz) = (GBC_SYS_CLK_FREQ * 10
kHz). This value is not available (will read 0) until 100us after a Board Reset, and is continually updated.
6.1.8
GBC_IRQ_STATUS
(R
EAD
/C
LEAR
)
This is a 64-bit interrupt status register for non-DMA interrupts. Each bit in this register corresponds to one of the Function Blocks; bit 0
corresponds to FB0 (whose ID and OFFSET are at 0x020), etc. Bits 60 through 63 are reserved. This is a Sticky Register, so the user clears it
by writing a ‘1’ to the appropriate bit.
6.1.9
GBC_DIRQ_STATUS
(R
EAD
/C
LEAR
)
This is a 64-bit interrupt status register for DMA interrupts. Each bit in this register corresponds to one of the Function Blocks; bit 0
corresponds to FB0 (whose ID and OFFSET are at 0x020), etc. Bits 60 through 63 are reserved. This is a “sticky” register, and the
user clears
it by writing
a ‘1’ to the appropriate bit.
6.1.10
FB
N
_ID
(R
EAD
-O
NLY
)
This is a 32-
bit value that identifies the type of Function Block in slot ‘n’.
0x01031000
–
ADC
0x01032000
–
DAC
0x01003001
–
Digital I/O
0x00010001
–
External Clocking
6.1.11
FB
N
_O
FFSET
(R
EAD
-O
NLY
)
This is the offset from the beginning of BAR2 that this Functional Block resides in.
6.1.12
FB
N
_O
FFSET
_DMA
(R
EAD
-O
NLY
)
This is the offset from the beginning of BAR2 that the Functional Block DMA Registers reside in.
