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29
DM35425HR User’s Manual
The Ready pin is set high when the Ready pin is set to output and the IN FIFO is not full.
5.6
External Clocking
The DM35425 features an external clocking function block. This feature allows the user to input a clock to drive a CLK_SRC_GLBn signal or
output a CLK_SRC_GLBn signal. The CLK_SRC_GLBn are used to drive the CLK_GLBn signal which are part of the FPGA function block
. Clock sources are used as either sample clocks for function blocks or triggers for starting and stopping them.
There are 6 available CLK_BUSn, each is associated with a pin on CN3. Each pin can be configured to be either an input or an output. As an
input to a CLK_SRC_GLBn, the max input clock frequency is ½ system clock frequency. This value can be found in
on page 32. As an output CLK_SRC_GLBn will generated on the associated pin. By default this signal will be a pulse that is high
for 25ns when the CLK_SRC_GLBn signal goes high. The width of this pulse can be increased using
on page
The following example show to capture ADC samples using an external and the external clocking function block:
External Clocking Function Block Setup
1.
Set the CLK_SRC_GLB2 as input (EXT_CLK_DIR)
2.
Set the edge detect of CLK_SRC_GLB2 (EXT_CLK_EDGE)
3.
Set CLK_SRC_GLB2 clocking method (EXT_CLK2_CFG)
4.
Provide clock on CN3 pin 39.
ADC Function Block Setup
1.
Set the ADC to the Uninitialized state (MODE = Uninitialized)
2.
Setup the DMA for the channel
3.
Set the input mode (CH_FRONT_END_CONFIG)
4.
Set the start and stop triggers (START_TRIG, STOP_TRIG)
5.
Set the clock source (CLK_SOURCE = CLK_BUS2)
6.
Set the sample rate (CLK_DIV_CNTR)
7.
Set the Pre and/or Post Capture counters (PRE_TRIGGER_CAPTURE, POST_STOP_CAPTURE)
8.
Set the ADC to the Reset state (MODE = Reset)
9.
Start the DMA
10.
Start the ADC (MODE = Go)
