RTD Embedded Technologies, Inc.
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25
DM35425HR User’s Manual
Each ADC channel supports a 511 sample FIFO for DMA. Each sample packed into a 32 bits word.
5.3.1
I
NITIALIZATION
There are several steps to initialize the Analog to Digital converter. The initialization prepares the converter and the front-end to capture
samples. Following the example programs and using the drivers provided by RTD will ensure that these steps are followed in the correct order.
Initialization of the ADC is performed as follows:
1.
Set the ADC to the Uninitialized state (MODE = Uninitialized)
2.
Setup the DMA for the channel
3.
Set the input mode (CH_FRONT_END_CONFIG)
4.
Set the start and stop triggers (START_TRIG, STOP_TRIG)
5.
Set the clock source (CLK_SOURCE)
6.
Set the sample rate (CLK_DIV_CNTR)
7.
Set the Pre and/or Post Capture counters (PRE_TRIGGER_CAPTURE, POST_STOP_CAPTURE)
8.
Set the ADC to the Reset state (MODE = Reset)
9.
Start the DMA
10.
Start the ADC (MODE = Go)
5.3.2
S
IMPLIFIED BLOCK DIAGRAM OF ANALOG INPUT
The following figure shows the front end circuit for the DM35425. It also shows the names of the FPGA registers in bold and the different ways
the front-end can be configured for different modes of operation. Refer to section
for more information about FPGA registers.
Single-Ended Input Mode
In single-ended mode, the input signal is measured in reference to the boards GND. In this mode the input signal is connected to input AIN0
through AIN31, and the low side to any of the GND pins available on the Analog Connector.
Differential Input Mode
In this mode your signal source may or may not have a separate ground reference. In differential mode, the high side input is measured in
reference to the low side input. In this mode you connect the high side of the input signal to the analog input, AIN0+
through
AIN16+, and
connect the low side to corresponding ADC
-
pin. In most cases, the board ground must still be attached to the device that is generating the
input signal.
When using the differential mode, you should install a 10 k
Ω
resistor pack at locations
RN2
and
RN18
on the DM35425HR to provide a
reference to ground for signal sources without a separate ground reference.
Full-Scale Input Range
The DM35425 has a programmable gain input per channel. This gain can be programed for 1,2,4,8 to achieve input ranges
±
5V,
±
2.5V,
±
1.25V,
±
0.625V.
M
ux
PGA
VREF
…
IN+
IN-
ADC: 12 Bit @
1.25 MSPS
To FPGA
Data
Out
AIN0/AIN0+
AIN1/AIN1+
AIN2/AIN2+
AIN3/AIN3+
CHn_Front_End_Config
[SE_DIFF]
CHn_Front_End_Config
[BIP_UNI]
CHn_Front_End_Config
[GAINSEL[2:0]]
AIN28/AIN12-
AIN29/AIN13-
AIN30/AIN14-
AIN31/AIN15-
