rtd DM35425, User Manual

Page: 4 / 60

RTD Embedded Technologies, Inc.
| www.rtd.com iv DM35425HR User’s Manual
Channel Delay 26
Effective Sampling Rate 26
5.4 Analog output ............................................................................................................................................................................ 27
5.4.1 Initializing the DAC Converter 27
5.4.2 Simplified block diagram of analog output 27
5.5 Advanced Digital I/O ................................................................................................................................................................. 28
DMA 28
Advanced Interrupts 28
Parallel Bus Mode 28
5.6 External Clocking ...................................................................................................................................................................... 29
6 Register Address Space 30
Register Types 30
Clock Source 30
6.1 BAR0 – General Board Control ................................................................................................................................................ 31
6.1.1 GBC_BRD_RST (Read/Write) 31
6.1.2 GBC_EOI (Read/Clear) 31
6.1.3 GBC_REV (Read-Only) 31
6.1.4 GBC_FMT (Read-Only) 31
6.1.5 GBC_PDP (Read-Only) 31
6.1.6 GBC_BUILD (Read-Only) 31
6.1.7 GBC_SYS_CLK_FREQ (Read Only) 32
6.1.8 GBC_IRQ_STATUS (Read/Clear) 32
6.1.9 GBC_DIRQ_STATUS (Read/Clear) 32
6.1.10 FBn_ID (Read-Only) 32
6.1.11 FBn_Offset (Read-Only) 32
6.1.12 FBn_Offset_DMA (Read-Only) 32
6.2 BAR2 – Functional Block Standard DMA ................................................................................................................................. 33
6.2.1 FB_DMAm_Action (Read/Write) 33
6.2.2 FB_DMAm_LAST_ACTION (READ/WRITE) 33
6.2.3 FB_DMAm_Setup (Read/Write) 34
6.2.4 FB_DMAm_Stat_Used (Read/Write) 34
6.2.5 FB_DMAm_Stat_Invalid (Read/Write) 34
6.2.6 FB_DMAm_Stat_Overflow (Read/Write) 34
6.2.7 FB_DMAm_Stat_Underflow (Read/Write) 34
6.2.8 FB_DMAm_Stat_Complete (Read/Write) 34
6.2.9 FB_DMAm_Current_Buffer (Read-Only) 34
6.2.10 FB_DMAm_COUNT (Read-Only) 34
6.2.11 FB_DMAm_RD_FIFO_CNT (Read-Only) 34
6.2.12 FB_DMAm_WR_FIFO_CNT (Read-Only) 35
6.2.13 FB_DMAm_ADDRESSn (Read/Write) 35
6.2.14 FB_DMAm_SIZEn (Read/Write) 35
6.2.15 FB_DMAm_CTRLn (Read/Write) 35
6.2.16 FB_DMAm_STATn (Read/Clear) 35
6.3 BAR2 – ADC Functional Block ................................................................................................................................................. 36
6.3.1 FB_ID (Read-Only) 36
6.3.2 FB_DMA_CHANNELS (Read -Only) 37
6.3.3 FB_DMA_BUFFERS (Read-Only) 37
6.3.4 Mode_Status (Read/Write, Read-Only) 37
6.3.5 CLK_SRC (Read/Write) 37
6.3.6 START_TRIG (Read/Write) 37
6.3.7 STOP_TRIG (Read/Write) 37
6.3.8 CLK_DIV (Read/Write) 37
6.3.9 CLK_DIV_CNTR (Read Only) 38
6.3.10 PRE_TRIGGER_CAPTURE (Read/Write) 38
6.3.11 POST_STOP_CAPTURE (Read/Write) 38
6.3.12 SAMPLE_CNT (Read Only) 38
6.3.13 INT_ENA (Maskable Read/Write) 38
6.3.14 INT_STAT (Read/Clear) 38
6.3.15 CLK_BUSn 38
6.3.16 CHn_FRONT_END_CONFIG (Maskable Read/Write) 39
6.3.17 CHn_FIFO_DATA_CNT (Read) 39
6.3.18 CHn_FILTER (Read/Write) 39