RTD Embedded Technologies, Inc.
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47
DM35425HR User’s Manual
o
0x03: Go, Re-arm. After converting the Post-Stop number of values, the triggering state machine is restarted. ADIO
data is resumed from that last value sent.
NOTE: In Parallel Bus Mode, unexpected results may occur when setting
Mode to GO before setting the VALID, CLK and READY bits on both
the Transmitter and Receiver
B[7:4]: Status
o
0x08: Uninitialized
–
The status when in the “Uninitialized” mode and the converter requires initialization.
o
0x09: Initializing
o
0x00: Stopped
–
The stat
us when in the “Reset” mode, or in the “Uninitialized” mode and the converter does not require
initialization.
o
0x01: Filling Pre-Trigger buffer
o
0x02: Waiting for start trigger
o
0x03: Sampling/Waiting for stop trigger
o
0x04: Filling Post-Stop buffer
o
0x05: Wait to re-arm
–
Waiting until local FIFO is empty so the pre-trigger buffer can be filled.
o
0x07: Done capturing
6.5.5
CLK_SRC
(R
EAD
/W
RITE
)
Selects the source for CLK_DIV from the clock bus.
Refer to
on page 30 for list of valid values.
6.5.6
START_TRIG
(R
EAD
/W
RITE
)
Selects the start trigger from the clock bus. CLK_DIV will start counting after the start trigger.
Refer to
on page 30 for list of valid values.
6.5.7
STOP_TRIG
(R
EAD
/W
RITE
)
Selects the stop trigger from the clock bus.
Refer to
on page 30 for list of valid values.
6.5.8
CLK_DIV
(R
EAD
/W
RITE
)
Divider for the pacer clock. Pacer Clock Frequency = (Clk_Src_Frequency) / (1 + CLK_DIV). If synchronizing with the pacer clock from
another Function Block (by using one of the CLK_BUS signals), this is typically set to 0.
NOTE: The max clock frequency for the ADIO FB is 4 MHz, CLK_DIV needs
set to a minimum of 9 for this FB to work properly.
6.5.9
CLK_DIV_CNTR
(R
EAD
O
NLY
)
The current value of the Clock Divide Counter. This counter starts at a value of CLK_DIV, and counts down. When it reaches zero, a sample
is taken. This is useful when using a slow sample clock.
